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| Presentation | 2007-11-21 16:10 Power analysis on Dynamic Reconfigurable Processor Takashi Nishimura, Yohei Hasegawa, Satoshi Tsutsumi, Hideharu Amano (Keio Univ.)  RECONF2007-41 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Dynamically Reconfigurable Processors have been expected to improve area and power eciency with the time-multiplexed execution using the run time reconfiguration compared with the traditional programmable devices such as FPGAs. Although some devices are commercially available recently, almost no efforts have been reported to analyze their power consumption, especially the additional power required for dynamic reconfiguration. Here, we analyzed the dynamic power consumption of MuCCRA-1, a prototype for the first step of developing a low power dynamically reconfigurable architecture. We reported the evaluation results for each hardware resource of the reconfigurable system. As the results, they shows about 60\% for processing, 20\% for clock tree, and 15\% for reconfiguration power on the benchmark streem application. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Dynamically Reconfigurable Processor / power analysis / / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 107, no. 341, RECONF2007-41, pp. 31-36, Nov. 2007. | |
| Paper # | RECONF2007-41 | |
| Date of Issue | 2007-11-14 (RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | RECONF2007-41 |
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| Conference Information | |
| Committee | VLD CPSY RECONF DC IPSJ-SLDM IPSJ-ARC |
| Conference Date | 2007-11-20 - 2007-11-22 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kitakyushu International Conference Center |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2007 ---A New Frontier in VLSI Design--- |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2007-11-VLD-CPSY-RECONF-DC-IPSJ-SLDM-IPSJ-ARC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Power analysis on Dynamic Reconfigurable Processor |
| Sub Title (in English) | |
| Keyword(1) | Dynamically Reconfigurable Processor |
| Keyword(2) | power analysis |
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| 1st Author's Name | Takashi Nishimura |
| 1st Author's Affiliation | Keio University (Keio Univ.) |
| 2nd Author's Name | Yohei Hasegawa |
| 2nd Author's Affiliation | Keio University (Keio Univ.) |
| 3rd Author's Name | Satoshi Tsutsumi |
| 3rd Author's Affiliation | Keio University (Keio Univ.) |
| 4th Author's Name | Hideharu Amano |
| 4th Author's Affiliation | Keio University (Keio Univ.) |
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| Speaker | Author-1 |
| Date Time | 2007-11-21 16:10:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | RECONF2007-41 |
| Volume (vol) | vol.107 |
| Number (no) | no.341 |
| Page | pp.31-36 |
| #Pages | 6 |
| Date of Issue | 2007-11-14 (RECONF) |
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