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Paper Abstract and Keywords
Presentation 2007-11-20 16:00
Track Swapping on Critical Paths Utilizing Random Variations for FPGAs to Enhance Speed and Yield
Yuuri Sugihara, Youhei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto Univ.) RECONF2007-34
Abstract (in Japanese) (See Japanese page) 
(in English) FPGAs in future deep submicron fabrication process will suffer from drastic speed and yield loss caused by device variations. We propose variation-aware reconfiguration which utilizes these variations for performance enhancement. We have fabricated and measured 90nm FPGAs, in which random variations without spatial correlations are dominant. To utilize these random variations for performance enhancement, optimizing each device from a common configuration is better than producing optimized configurations according to detailed measurement results. In this paper we apply the track swapping procedure to critical path reconfiguration which obtains an optimized configuration to repeat measurement and reconfiguration. First we configure all fabricated FPGAs with a common configuration data. The configuration of each die is optimized to reroute the critical paths that does not meet timing specifications. Rerouting of a critical path usually causes drastic topology changes which may prolong other paths and will create new critical paths. In the track swapping procedure, we swap a wire track on a critical path for the adjacent track without any topology change. It can be realized to use switch blocks with more flexibility. We experiment performance enhancement by applying the track swapping to LGSynth93 benchmark circuits. We achieve 5.81% of speed enhancement and 26.62% of yield enhancement.
Keyword (in Japanese) (See Japanese page) 
(in English) Variation / FPGA / Reconfigure / Yield / / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 340, RECONF2007-34, pp. 13-18, Nov. 2007.
Paper # RECONF2007-34 
Date of Issue 2007-11-13 (RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee VLD CPSY RECONF DC IPSJ-SLDM IPSJ-ARC  
Conference Date 2007-11-20 - 2007-11-22 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitakyushu International Conference Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2007 ---A New Frontier in VLSI Design--- 
Paper Information
Registration To RECONF 
Conference Code 2007-11-VLD-CPSY-RECONF-DC-IPSJ-SLDM-IPSJ-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Track Swapping on Critical Paths Utilizing Random Variations for FPGAs to Enhance Speed and Yield 
Sub Title (in English)  
Keyword(1) Variation  
Keyword(2) FPGA  
Keyword(3) Reconfigure  
Keyword(4) Yield  
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1st Author's Name Yuuri Sugihara  
1st Author's Affiliation Kyoto University (Kyoto Univ.)
2nd Author's Name Youhei Kume  
2nd Author's Affiliation Kyoto University (Kyoto Univ.)
3rd Author's Name Kazutoshi Kobayashi  
3rd Author's Affiliation Kyoto University (Kyoto Univ.)
4th Author's Name Hidetoshi Onodera  
4th Author's Affiliation Kyoto University (Kyoto Univ.)
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Speaker Author-1 
Date Time 2007-11-20 16:00:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # RECONF2007-34 
Volume (vol) vol.107 
Number (no) no.340 
Page pp.13-18 
#Pages
Date of Issue 2007-11-13 (RECONF) 


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