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| Presentation | 2007-11-20 11:20 Proposal of domino-RSL circuit which is resistant to Differential Power Analysis attack on cryptographic circuit Yoshinobu Toyoda, Kenta Kido, Yoshiaki Shitabayashi, Takeshi Fujino (Ritsumeikan Univ.)  VLD2007-77 DC2007-32 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Countermeasures against Side Channel Attack are necessary to achieve cryptographic circuit that has tamper resistance. Many countermeasures, especially against DPA (Differential Power Analysis), are proposed because DPA is the most effective attack to estimate cipher key. RSL (Random Switching Logic) method that makes transition probability at each gate 1/2 using random value is proposed as a countermeasure at primitive gate level. The method is effective against DPA, but requires enable signal that controls drive timing at each gate to achieve hazard-free circuits. Therefore, the circuit becomes complex. In this paper, we propose domino-RSL circuit that achieves operation similar to RSL with the domino logic. The circuit doesn’t require enable signal because domino logic is hazard-free. We evaluated our method about security against DPA and area of circuit using multiplier in Galois field. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Side Channel Attack / DPA / RSL / domino logic / Galois field / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 107, no. 334, VLD2007-77, pp. 43-48, Nov. 2007. | |
| Paper # | VLD2007-77 | |
| Date of Issue | 2007-11-13 (VLD, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2007-77 DC2007-32 |
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| Conference Information | |
| Committee | VLD CPSY RECONF DC IPSJ-SLDM IPSJ-ARC |
| Conference Date | 2007-11-20 - 2007-11-22 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kitakyushu International Conference Center |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2007 ---A New Frontier in VLSI Design--- |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2007-11-VLD-CPSY-RECONF-DC-IPSJ-SLDM-IPSJ-ARC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Proposal of domino-RSL circuit which is resistant to Differential Power Analysis attack on cryptographic circuit |
| Sub Title (in English) | |
| Keyword(1) | Side Channel Attack |
| Keyword(2) | DPA |
| Keyword(3) | RSL |
| Keyword(4) | domino logic |
| Keyword(5) | Galois field |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Yoshinobu Toyoda |
| 1st Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
| 2nd Author's Name | Kenta Kido |
| 2nd Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
| 3rd Author's Name | Yoshiaki Shitabayashi |
| 3rd Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
| 4th Author's Name | Takeshi Fujino |
| 4th Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
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| Speaker | Author-1 |
| Date Time | 2007-11-20 11:20:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2007-77, DC2007-32 |
| Volume (vol) | vol.107 |
| Number (no) | no.334(VLD), no.337(DC) |
| Page | pp.43-48 |
| #Pages | 6 |
| Date of Issue | 2007-11-13 (VLD, DC) |
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