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Paper Abstract and Keywords
Presentation 2007-11-20 15:35
A Study of Conection Block Structure and Implementation Methods of Multi-Input Functions for Variable Grain Logic Cell
Kazunori Matsuyama, Ryoichi Yamaguchi, Yoshiaki Satou, Hiroshi Miura, Masahiro Koga, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2007-33
Abstract (in Japanese) (See Japanese page) 
(in English) Since VGLC(Variable Grain Logic Cell) has a feature set both coarse-grained and fine-grained
types, its structure can be varied according to various computations in an application.
VGLC can be implemented all of 2,3,4-input logic functions.
However, when we forcus on its architecture, not only under 4-input but over 5-input
logic functions can be implemented in one VGLC. In order to consider this case, it is necessary to use boolean
matching method with logic functions of a mapping circuit. This paper shows mapping method
with VGLC, and evaluates area and delay. As a result, the area is decreased by 58.9\%, and
the delay is reduced by 25.9\% in the benchmark circuits.
Keyword (in Japanese) (See Japanese page) 
(in English) reconfigurable logic device / coarse-grain / fine-grain / multiple inputs logic / boolean matching / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 340, RECONF2007-33, pp. 7-12, Nov. 2007.
Paper # RECONF2007-33 
Date of Issue 2007-11-13 (RECONF) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF RECONF2007-33

Conference Information
Committee VLD CPSY RECONF DC IPSJ-SLDM IPSJ-ARC  
Conference Date 2007-11-20 - 2007-11-22 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitakyushu International Conference Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2007 ---A New Frontier in VLSI Design--- 
Paper Information
Registration To RECONF 
Conference Code 2007-11-VLD-CPSY-RECONF-DC-IPSJ-SLDM-IPSJ-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Study of Conection Block Structure and Implementation Methods of Multi-Input Functions for Variable Grain Logic Cell 
Sub Title (in English)  
Keyword(1) reconfigurable logic device  
Keyword(2) coarse-grain  
Keyword(3) fine-grain  
Keyword(4) multiple inputs logic  
Keyword(5) boolean matching  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Kazunori Matsuyama  
1st Author's Affiliation Kumamoto University (Kumamoto Univ.)
2nd Author's Name Ryoichi Yamaguchi  
2nd Author's Affiliation Kumamoto University (Kumamoto Univ.)
3rd Author's Name Yoshiaki Satou  
3rd Author's Affiliation Kumamoto University (Kumamoto Univ.)
4th Author's Name Hiroshi Miura  
4th Author's Affiliation Kumamoto University (Kumamoto Univ.)
5th Author's Name Masahiro Koga  
5th Author's Affiliation Kumamoto University (Kumamoto Univ.)
6th Author's Name Kazuki Inoue  
6th Author's Affiliation Kumamoto University (Kumamoto Univ.)
7th Author's Name Motoki Amagasaki  
7th Author's Affiliation Kumamoto University (Kumamoto Univ.)
8th Author's Name Masahiro Iida  
8th Author's Affiliation Kumamoto University (Kumamoto Univ.)
9th Author's Name Toshinori Sueyoshi  
9th Author's Affiliation Kumamoto University (Kumamoto Univ.)
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Speaker
Date Time 2007-11-20 15:35:00 
Presentation Time 25 
Registration for RECONF 
Paper # IEICE-RECONF2007-33 
Volume (vol) IEICE-107 
Number (no) no.340 
Page pp.7-12 
#Pages IEICE-6 
Date of Issue IEICE-RECONF-2007-11-13 


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