Paper Abstract and Keywords |
Presentation |
2007-10-25 15:50
Acceleration of AES Encryption with CAM-Enhanced Massive-Parallel SIMD Matrix Processor Masakatsu Ishizaki, Takeshi Kumaki, Masaharu Tagami, Tetsushi Koide, Hans Juergen Mattausch (Hiroshima Univ.), Takayuki Gyohten, Hideyuki Noda, Yoshihiro Okuno, Kazutami Arimoto (Renesas Technology) CPSY2007-28 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
We have previously reported that the Content Addressable Memory (CAM)-enhanced massive-parallel Single Instruction Multiple Data (SIMD) matrix processor has the capability of high-speed data processing for common multimedia algorithms such as JPEG.
In this paper, we propose an effective implementation of the Advanced Encryption Standard (AES) with a CAM-enhanced massive-parallel SIMD matrix processor. The AES is the common encryption algorithm which was selected by the National Institute of Standards and Technology (NIST) in U.S.A. The determined performance in throughput in the AES- Cipher Block Chaining (CBC) mode is 207.68Mbps, and throughput per area is 54.68 Mbps/${mm^2}$. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
SIMD / CAM / AES / Multimedia / massive-parallel SIMD Matrix Processor / block-cipher / / |
Reference Info. |
IEICE Tech. Rep., vol. 107, no. 276, CPSY2007-28, pp. 25-30, Oct. 2007. |
Paper # |
CPSY2007-28 |
Date of Issue |
2007-10-18 (CPSY) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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CPSY2007-28 |
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