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Paper Abstract and Keywords
Presentation 2007-10-25 15:50
Acceleration of AES Encryption with CAM-Enhanced Massive-Parallel SIMD Matrix Processor
Masakatsu Ishizaki, Takeshi Kumaki, Masaharu Tagami, Tetsushi Koide, Hans Juergen Mattausch (Hiroshima Univ.), Takayuki Gyohten, Hideyuki Noda, Yoshihiro Okuno, Kazutami Arimoto (Renesas Technology) CPSY2007-28
Abstract (in Japanese) (See Japanese page) 
(in English) We have previously reported that the Content Addressable Memory (CAM)-enhanced massive-parallel Single Instruction Multiple Data (SIMD) matrix processor has the capability of high-speed data processing for common multimedia algorithms such as JPEG.

In this paper, we propose an effective implementation of the Advanced Encryption Standard (AES) with a CAM-enhanced massive-parallel SIMD matrix processor. The AES is the common encryption algorithm which was selected by the National Institute of Standards and Technology (NIST) in U.S.A. The determined performance in throughput in the AES- Cipher Block Chaining (CBC) mode is 207.68Mbps, and throughput per area is 54.68 Mbps/${mm^2}$.
Keyword (in Japanese) (See Japanese page) 
(in English) SIMD / CAM / AES / Multimedia / massive-parallel SIMD Matrix Processor / block-cipher / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 276, CPSY2007-28, pp. 25-30, Oct. 2007.
Paper # CPSY2007-28 
Date of Issue 2007-10-18 (CPSY) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee CPSY  
Conference Date 2007-10-25 - 2007-10-26 
Place (in Japanese) (See Japanese page) 
Place (in English) Kumamoto University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Advanced Computer Systems, etc. 
Paper Information
Registration To CPSY 
Conference Code 2007-10-CPSY 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Acceleration of AES Encryption with CAM-Enhanced Massive-Parallel SIMD Matrix Processor 
Sub Title (in English)  
Keyword(1) SIMD  
Keyword(2) CAM  
Keyword(3) AES  
Keyword(4) Multimedia  
Keyword(5) massive-parallel SIMD Matrix Processor  
Keyword(6) block-cipher  
Keyword(7)  
Keyword(8)  
1st Author's Name Masakatsu Ishizaki  
1st Author's Affiliation Hiroshima University (Hiroshima Univ.)
2nd Author's Name Takeshi Kumaki  
2nd Author's Affiliation Hiroshima University (Hiroshima Univ.)
3rd Author's Name Masaharu Tagami  
3rd Author's Affiliation Hiroshima University (Hiroshima Univ.)
4th Author's Name Tetsushi Koide  
4th Author's Affiliation Hiroshima University (Hiroshima Univ.)
5th Author's Name Hans Juergen Mattausch  
5th Author's Affiliation Hiroshima University (Hiroshima Univ.)
6th Author's Name Takayuki Gyohten  
6th Author's Affiliation Renesas Technology Corp. (Renesas Technology)
7th Author's Name Hideyuki Noda  
7th Author's Affiliation Renesas Technology Corp. (Renesas Technology)
8th Author's Name Yoshihiro Okuno  
8th Author's Affiliation Renesas Technology Corp. (Renesas Technology)
9th Author's Name Kazutami Arimoto  
9th Author's Affiliation Renesas Technology Corp. (Renesas Technology)
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Speaker Author-1 
Date Time 2007-10-25 15:50:00 
Presentation Time 40 minutes 
Registration for CPSY 
Paper # CPSY2007-28 
Volume (vol) vol.107 
Number (no) no.276 
Page pp.25-30 
#Pages
Date of Issue 2007-10-18 (CPSY) 


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