Paper Abstract and Keywords |
Presentation |
2007-08-24 09:20
An On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise Yasumi Nakamura, Makoto Takamiya, Takayasu Sakurai (Univ. of Tokyo) SDM2007-157 ICD2007-85 Link to ES Tech. Rep. Archives: SDM2007-157 ICD2007-85 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
An on-chip noise canceller with high voltage supply lines for the nanosecond-range power supply noise is proposed. The canceller fabricated with 90-nm CMOS achieves 68% noise reduction with 2.0% power increase. Under the same noise reduction conditions, the area penalty for the canceller is 1/77 and 1/45 of those for the additional on-chip decoupling capacitors and the power supply lines respectively. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Noise Canceller / Power Integrity / VLSI / Power Supply / High Voltage / Decoupling / Nanosecond / |
Reference Info. |
IEICE Tech. Rep., vol. 107, no. 195, ICD2007-85, pp. 91-94, Aug. 2007. |
Paper # |
ICD2007-85 |
Date of Issue |
2007-08-16 (SDM, ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
SDM2007-157 ICD2007-85 Link to ES Tech. Rep. Archives: SDM2007-157 ICD2007-85 |
Conference Information |
Committee |
ICD SDM |
Conference Date |
2007-08-23 - 2007-08-24 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kitami Institute of Technology |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
VLSI Circuit and Device Technologies (High Speed, Low Voltage, and Low Power Consumption) |
Paper Information |
Registration To |
ICD |
Conference Code |
2007-08-ICD-SDM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
An On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise |
Sub Title (in English) |
|
Keyword(1) |
Noise Canceller |
Keyword(2) |
Power Integrity |
Keyword(3) |
VLSI |
Keyword(4) |
Power Supply |
Keyword(5) |
High Voltage |
Keyword(6) |
Decoupling |
Keyword(7) |
Nanosecond |
Keyword(8) |
|
1st Author's Name |
Yasumi Nakamura |
1st Author's Affiliation |
University of Tokyo (Univ. of Tokyo) |
2nd Author's Name |
Makoto Takamiya |
2nd Author's Affiliation |
University of Tokyo (Univ. of Tokyo) |
3rd Author's Name |
Takayasu Sakurai |
3rd Author's Affiliation |
University of Tokyo (Univ. of Tokyo) |
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Speaker |
1 |
Date Time |
2007-08-24 09:20:00 |
Presentation Time |
25 |
Registration for |
ICD |
Paper # |
IEICE-SDM2007-157,IEICE-ICD2007-85 |
Volume (vol) |
IEICE-107 |
Number (no) |
no.194(SDM), no.195(ICD) |
Page |
pp.91-94 |
#Pages |
IEICE-4 |
Date of Issue |
IEICE-SDM-2007-08-16,IEICE-ICD-2007-08-16 |
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