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| Presentation | 2007-08-24 15:40 An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi (Kobe Univ.), Koji Nii (Kobe Univ./Renesas Technology), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.)  SDM2007-167 ICD2007-95 Link to ES Tech. Rep. Archives: SDM2007-167 ICD2007-95 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This paper demonstrates that an 8T memory cell can be alternative design to a 6T cell in a future highly-integrated SRAM, in a 45-nm process and later with large threshold-voltage variation. The proposed voltage-control scheme that improves a write margin and read current, and the write-back scheme that stabilizes unselected cells are applied to the 8T SRAM. We verified that the low-voltage operation at 0.42 V in a 90-nm 64-Mb SRAM is possible under dynamic voltage scaling (DVS) environment. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | SRAM / 6T / 8T / DVS / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 107, no. 195, ICD2007-95, pp. 139-144, Aug. 2007. | |
| Paper # | ICD2007-95 | |
| Date of Issue | 2007-08-16 (SDM, ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | SDM2007-167 ICD2007-95 Link to ES Tech. Rep. Archives: SDM2007-167 ICD2007-95 |
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| Conference Information | |
| Committee | ICD SDM |
| Conference Date | 2007-08-23 - 2007-08-24 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kitami Institute of Technology |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | VLSI Circuit and Device Technologies (High Speed, Low Voltage, and Low Power Consumption) |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2007-08-ICD-SDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment |
| Sub Title (in English) | |
| Keyword(1) | SRAM |
| Keyword(2) | 6T |
| Keyword(3) | 8T |
| Keyword(4) | DVS |
| Keyword(5) | |
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| 1st Author's Name | Yasuhiro Morita |
| 1st Author's Affiliation | Kobe University (Kobe Univ.) |
| 2nd Author's Name | Hidehiro Fujiwara |
| 2nd Author's Affiliation | Kobe University (Kobe Univ.) |
| 3rd Author's Name | Hiroki Noguchi |
| 3rd Author's Affiliation | Kobe University (Kobe Univ.) |
| 4th Author's Name | Yusuke Iguchi |
| 4th Author's Affiliation | Kobe University (Kobe Univ.) |
| 5th Author's Name | Koji Nii |
| 5th Author's Affiliation | Kobe University/Renesas Technology (Kobe Univ./Renesas Technology) |
| 6th Author's Name | Hiroshi Kawaguchi |
| 6th Author's Affiliation | Kobe University (Kobe Univ.) |
| 7th Author's Name | Masahiko Yoshimoto |
| 7th Author's Affiliation | Kobe University (Kobe Univ.) |
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| Speaker | Author-1 |
| Date Time | 2007-08-24 15:40:00 |
| Presentation Time | 25 minutes |
| Registration for | ICD |
| Paper # | SDM2007-167, ICD2007-95 |
| Volume (vol) | vol.107 |
| Number (no) | no.194(SDM), no.195(ICD) |
| Page | pp.139-144 |
| #Pages | 6 |
| Date of Issue | 2007-08-16 (SDM, ICD) |
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