IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
... (for ESS/CS/ES/ISS)
Tech. Rep. Archives
... (for ES/CS)
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2007-08-24 13:50
Design of High Density LSI with Three-Dimensional Transistor FinFET -- Effect of Pattern Area Reduction with CMOS Cell Library --
Keisuke Okamoto, Keisuke Koizumi, Yu Hiroshima, Shigeyoshi Watanabe (SIT) SDM2007-163 ICD2007-91 Link to ES Tech. Rep. Archives: SDM2007-163 ICD2007-91
Abstract (in Japanese) (See Japanese page) 
(in English) New design method of system LSI with FinFET has been developed. Using planar+FinFET architecture the pattern area of CMOS cell library can be reduced to about 40% compared with the conventional planar case. New design method is a promising candidate for realizing future high performance, high-density system LSI.
Keyword (in Japanese) (See Japanese page) 
(in English) system LSI / Three-Dimensional Transistor / FinFET / channel width / sidewall channel width / cell library / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 195, ICD2007-91, pp. 119-124, Aug. 2007.
Paper # ICD2007-91 
Date of Issue 2007-08-16 (SDM, ICD) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
and
reproduction
技術研究報告に掲載された論文の著作権はIEICEに帰属します.(許諾番号:10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SDM2007-163 ICD2007-91 Link to ES Tech. Rep. Archives: SDM2007-163 ICD2007-91

Conference Information
Committee ICD SDM  
Conference Date 2007-08-23 - 2007-08-24 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitami Institute of Technology 
Topics (in Japanese) (See Japanese page) 
Topics (in English) VLSI Circuit and Device Technologies (High Speed, Low Voltage, and Low Power Consumption) 
Paper Information
Registration To ICD 
Conference Code 2007-08-ICD-SDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design of High Density LSI with Three-Dimensional Transistor FinFET 
Sub Title (in English) Effect of Pattern Area Reduction with CMOS Cell Library 
Keyword(1) system LSI  
Keyword(2) Three-Dimensional Transistor  
Keyword(3) FinFET  
Keyword(4) channel width  
Keyword(5) sidewall channel width  
Keyword(6) cell library  
Keyword(7)  
Keyword(8)  
1st Author's Name Keisuke Okamoto  
1st Author's Affiliation Shonan Institute of Technology (SIT)
2nd Author's Name Keisuke Koizumi  
2nd Author's Affiliation Shonan Institute of Technology (SIT)
3rd Author's Name Yu Hiroshima  
3rd Author's Affiliation Shonan Institute of Technology (SIT)
4th Author's Name Shigeyoshi Watanabe  
4th Author's Affiliation Shonan Institute of Technology (SIT)
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker
Date Time 2007-08-24 13:50:00 
Presentation Time 25 
Registration for ICD 
Paper # IEICE-SDM2007-163,IEICE-ICD2007-91 
Volume (vol) IEICE-107 
Number (no) no.194(SDM), no.195(ICD) 
Page pp.119-124 
#Pages IEICE-6 
Date of Issue IEICE-SDM-2007-08-16,IEICE-ICD-2007-08-16 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan