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Paper Abstract and Keywords
Presentation 2007-08-23 08:55
Homogenous Dual-Processor core with Shared L1 Cache for Mobile Multimedia SoC
Tetsu Hosoki, Takao Yamamoto, Masayuki Yamasaki, Keisuke Kaneko, Masaitsu Nakajima (Matsushita Electric Industrial Co., Ltd.) SDM2007-142 ICD2007-70 Link to ES Tech. Rep. Archives: SDM2007-142 ICD2007-70
Abstract (in Japanese) (See Japanese page) 
(in English) We propose a novel dual-processor core which adopts a shared L1 cache with active way scheme. In this scheme, each way of cache is owned by specific thread or processor and replace operation is only happened to its own ways. By implementing 2 stages cache access with this scheme, this structure only requires dual port TAG, and no dual port DATA memory to realize simultaneous access from both processors. This architecture can guarantee no cache thrashing and no snoop overhead. And also by sharing cache memory and cache controller, power dissipation is 23% smaller in case of heavy load and area is 29 % smaller than dual processor core with snoop cache.
Keyword (in Japanese) (See Japanese page) 
(in English) Homogeneous / Dual-processor / Snoop cache / Shared cache / Low power / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 195, ICD2007-70, pp. 5-9, Aug. 2007.
Paper # ICD2007-70 
Date of Issue 2007-08-16 (SDM, ICD) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
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技術研究報告に掲載された論文の著作権はIEICEに帰属します.(許諾番号:10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SDM2007-142 ICD2007-70 Link to ES Tech. Rep. Archives: SDM2007-142 ICD2007-70

Conference Information
Committee ICD SDM  
Conference Date 2007-08-23 - 2007-08-24 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitami Institute of Technology 
Topics (in Japanese) (See Japanese page) 
Topics (in English) VLSI Circuit and Device Technologies (High Speed, Low Voltage, and Low Power Consumption) 
Paper Information
Registration To ICD 
Conference Code 2007-08-ICD-SDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Homogenous Dual-Processor core with Shared L1 Cache for Mobile Multimedia SoC 
Sub Title (in English)  
Keyword(1) Homogeneous  
Keyword(2) Dual-processor  
Keyword(3) Snoop cache  
Keyword(4) Shared cache  
Keyword(5) Low power  
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1st Author's Name Tetsu Hosoki  
1st Author's Affiliation Matsushita Electric Industrial Co., Ltd. (Matsushita Electric Industrial Co., Ltd.)
2nd Author's Name Takao Yamamoto  
2nd Author's Affiliation Matsushita Electric Industrial Co., Ltd. (Matsushita Electric Industrial Co., Ltd.)
3rd Author's Name Masayuki Yamasaki  
3rd Author's Affiliation Matsushita Electric Industrial Co., Ltd. (Matsushita Electric Industrial Co., Ltd.)
4th Author's Name Keisuke Kaneko  
4th Author's Affiliation Matsushita Electric Industrial Co., Ltd. (Matsushita Electric Industrial Co., Ltd.)
5th Author's Name Masaitsu Nakajima  
5th Author's Affiliation Matsushita Electric Industrial Co., Ltd. (Matsushita Electric Industrial Co., Ltd.)
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Speaker
Date Time 2007-08-23 08:55:00 
Presentation Time 25 
Registration for ICD 
Paper # IEICE-SDM2007-142,IEICE-ICD2007-70 
Volume (vol) IEICE-107 
Number (no) no.194(SDM), no.195(ICD) 
Page pp.5-9 
#Pages IEICE-5 
Date of Issue IEICE-SDM-2007-08-16,IEICE-ICD-2007-08-16 


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