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| Presentation | 2007-08-23 15:25 A 1.92us-wake-up time thick-gate-oxide power switch technique for ultra low-power single-chip mobile processors Kazuki Fukuoka, Osamu Ozawa, Ryo Mori, Yasuto Igarashi, Toshio Sasaki, Takashi Kuraishi, Yoshihiko Yasu, Koichiro Ishibashi (Renesas Technology)  SDM2007-153 ICD2007-81 Link to ES Tech. Rep. Archives: SDM2007-153 ICD2007-81 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | A technique for controlling rush current and wake-up time of thick-gate-oxide power switches is described. Suppressing the variation of rush current on PVT allows shorter wake-up times, which can reduce leakage currents in a mobile processor. Wake-up takes 1.92us and leakage current is reduced by 96.9% in an application CPU domain. Probing the rush current indicated accurate control by the technique. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | thick-gate-oxide power switch / fast wake-up / leakage current reduction / rush current / PVT variation / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 107, no. 195, ICD2007-81, pp. 69-73, Aug. 2007. | |
| Paper # | ICD2007-81 | |
| Date of Issue | 2007-08-16 (SDM, ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | SDM2007-153 ICD2007-81 Link to ES Tech. Rep. Archives: SDM2007-153 ICD2007-81 |
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| Conference Information | |
| Committee | ICD SDM |
| Conference Date | 2007-08-23 - 2007-08-24 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kitami Institute of Technology |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | VLSI Circuit and Device Technologies (High Speed, Low Voltage, and Low Power Consumption) |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2007-08-ICD-SDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A 1.92us-wake-up time thick-gate-oxide power switch technique for ultra low-power single-chip mobile processors |
| Sub Title (in English) | |
| Keyword(1) | thick-gate-oxide power switch |
| Keyword(2) | fast wake-up |
| Keyword(3) | leakage current reduction |
| Keyword(4) | rush current |
| Keyword(5) | PVT variation |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Kazuki Fukuoka |
| 1st Author's Affiliation | Renesas Technology Corp. (Renesas Technology) |
| 2nd Author's Name | Osamu Ozawa |
| 2nd Author's Affiliation | Renesas Technology Corp. (Renesas Technology) |
| 3rd Author's Name | Ryo Mori |
| 3rd Author's Affiliation | Renesas Technology Corp. (Renesas Technology) |
| 4th Author's Name | Yasuto Igarashi |
| 4th Author's Affiliation | Renesas Technology Corp. (Renesas Technology) |
| 5th Author's Name | Toshio Sasaki |
| 5th Author's Affiliation | Renesas Technology Corp. (Renesas Technology) |
| 6th Author's Name | Takashi Kuraishi |
| 6th Author's Affiliation | Renesas Technology Corp. (Renesas Technology) |
| 7th Author's Name | Yoshihiko Yasu |
| 7th Author's Affiliation | Renesas Technology Corp. (Renesas Technology) |
| 8th Author's Name | Koichiro Ishibashi |
| 8th Author's Affiliation | Renesas Technology Corp. (Renesas Technology) |
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| Speaker | Author-1 |
| Date Time | 2007-08-23 15:25:00 |
| Presentation Time | 25 minutes |
| Registration for | ICD |
| Paper # | SDM2007-153, ICD2007-81 |
| Volume (vol) | vol.107 |
| Number (no) | no.194(SDM), no.195(ICD) |
| Page | pp.69-73 |
| #Pages | 5 |
| Date of Issue | 2007-08-16 (SDM, ICD) |
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