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Paper Abstract and Keywords
Presentation 2007-08-23 11:35
A Periodically All-in-Phase Clocking Architecture for Multi-Core SOC Platforms
Atsufumi Shibayama, Koichi Nose, Sunao Torii, Masayuki Mizuno, Masato Edahiro (NEC) SDM2007-147 ICD2007-75 Link to ES Tech. Rep. Archives: SDM2007-147 ICD2007-75
Abstract (in Japanese) (See Japanese page) 
(in English) Methods for clock generation, distribution, and synchronization in system-on-chip (SOC) designs have become important issues because the number of cores in SOCs has increased and these cores require individual clocks of varying frequencies. A periodically all-in-phase clock generator and a skew-tolerant bus wrapper have been developed for multi-core SOC platforms. The clock generator produces clock frequencies in 81-steps, and the bus wrapper makes possible deterministic data transfer among different frequency clocks even when inter-clock skew is as high as 2 clock cycle times. A combination of the clock generator, the bus wrapper, and loosely balanced global clock distribution serves to ease chip-timing design while maintaining deterministic chip behavior.
Keyword (in Japanese) (See Japanese page) 
(in English) multi-core / system-on-chip / SOC / clock / synchronization / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 195, ICD2007-75, pp. 35-40, Aug. 2007.
Paper # ICD2007-75 
Date of Issue 2007-08-16 (SDM, ICD) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SDM2007-147 ICD2007-75 Link to ES Tech. Rep. Archives: SDM2007-147 ICD2007-75

Conference Information
Committee ICD SDM  
Conference Date 2007-08-23 - 2007-08-24 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitami Institute of Technology 
Topics (in Japanese) (See Japanese page) 
Topics (in English) VLSI Circuit and Device Technologies (High Speed, Low Voltage, and Low Power Consumption) 
Paper Information
Registration To ICD 
Conference Code 2007-08-ICD-SDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Periodically All-in-Phase Clocking Architecture for Multi-Core SOC Platforms 
Sub Title (in English)  
Keyword(1) multi-core  
Keyword(2) system-on-chip  
Keyword(3) SOC  
Keyword(4) clock  
Keyword(5) synchronization  
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1st Author's Name Atsufumi Shibayama  
1st Author's Affiliation NEC Corporation (NEC)
2nd Author's Name Koichi Nose  
2nd Author's Affiliation NEC Corporation (NEC)
3rd Author's Name Sunao Torii  
3rd Author's Affiliation NEC Corporation (NEC)
4th Author's Name Masayuki Mizuno  
4th Author's Affiliation NEC Corporation (NEC)
5th Author's Name Masato Edahiro  
5th Author's Affiliation NEC Corporation (NEC)
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Speaker
Date Time 2007-08-23 11:35:00 
Presentation Time 25 
Registration for ICD 
Paper # IEICE-SDM2007-147,IEICE-ICD2007-75 
Volume (vol) IEICE-107 
Number (no) no.194(SDM), no.195(ICD) 
Page pp.35-40 
#Pages IEICE-6 
Date of Issue IEICE-SDM-2007-08-16,IEICE-ICD-2007-08-16 


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