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Paper Abstract and Keywords
Presentation 2007-08-02 09:00
Higer Performace Architecture of FDTD/FIT Memory Machine
Yoshiyuki Fujishima, Yuya Fujita, Hideki Kawaguchi (Muroran IT), Shun-suke Matsuoka (Asahikawa NCT) MW2007-42 OPE2007-29 Link to ES Tech. Rep. Archives: MW2007-42 OPE2007-29
Abstract (in Japanese) (See Japanese page) 
(in English) To achieve efficient design environment of electrical products based on microwave technologies, the authors have been working in development of a dedicated computer for 3D microwave electromagnetic fields simulation. There are two kinds of architectures that are oriented to high performance computations and very larger scale simulations. In this paper, a higher performance architecture of the larger scale simulation architecture computer is propose and also VHDL simulations of the propose architecture are shown.
Keyword (in Japanese) (See Japanese page) 
(in English) Microwave simulator / Dedicated computer / FDTD method / Data flow machine / High performance computing / / /  
Reference Info. IEICE Tech. Rep., vol. 107, Aug. 2007.
Paper #  
Date of Issue 2007-07-26 (MW, OPE) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
and
reproduction
技術研究報告に掲載された論文の著作権はIEICEに帰属します.(許諾番号:10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF MW2007-42 OPE2007-29 Link to ES Tech. Rep. Archives: MW2007-42 OPE2007-29

Conference Information
Committee EMT OPE MW  
Conference Date 2007-08-02 - 2007-08-03 
Place (in Japanese) (See Japanese page) 
Place (in English) Muroran Institute of Technology 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To EMT 
Conference Code 2007-08-EMT-OPE-MW 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Higer Performace Architecture of FDTD/FIT Memory Machine 
Sub Title (in English)  
Keyword(1) Microwave simulator  
Keyword(2) Dedicated computer  
Keyword(3) FDTD method  
Keyword(4) Data flow machine  
Keyword(5) High performance computing  
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1st Author's Name Yoshiyuki Fujishima  
1st Author's Affiliation Muroran Institute of Technology (Muroran IT)
2nd Author's Name Yuya Fujita  
2nd Author's Affiliation Muroran Institute of Technology (Muroran IT)
3rd Author's Name Hideki Kawaguchi  
3rd Author's Affiliation Muroran Institute of Technology (Muroran IT)
4th Author's Name Shun-suke Matsuoka  
4th Author's Affiliation Asahikawa National College of Technology (Asahikawa NCT)
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Speaker
Date Time 2007-08-02 09:00:00 
Presentation Time 25 
Registration for EMT 
Paper # IEICE-MW2007-42,IEICE-OPE2007-29 
Volume (vol) IEICE-107 
Number (no) no.172(MW), no.173(OPE) 
Page pp.1-6 
#Pages IEICE-6 
Date of Issue IEICE-MW-2007-07-26,IEICE-OPE-2007-07-26 


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