講演抄録/キーワード |
講演名 |
2007-07-27 16:55
Studies on the Phase Noise and Spurious Level Behavior of an All Digital Phase Locked Loop ○Michael Zamrowski(Johannes Gutenberg Univ.)・Tsuyoshi Terao・Kiyomichi Araki(Tokyo Inst. of Tech.) SR2007-45 |
抄録 |
(和) |
An All Digital Phase Locked Loop (ADPLL) was proposed being suitable for a CMOS processed system on one chip digital RF transceiver. We analyzed the phase noise and the spurious behavior of the ADPLL depending on the components like the Digital Controlled Oscillator (DCO), the Time to Digital Converter (TDC), and the Loop filter. We also investigated the relation between the latch-up time and the phase noise and the spurious level. We attempted to verify the analysis results with the former simulation results. |
(英) |
An All Digital Phase Locked Loop (ADPLL) was proposed being suitable for a CMOS processed system on one chip digital RF transceiver. We analyzed the phase noise and the spurious behavior of the ADPLL depending on the components like the Digital Controlled Oscillator (DCO), the Time to Digital Converter (TDC), and the Loop filter. We also investigated the relation between the latch-up time and the phase noise and the spurious level. We attempted to verify the analysis results with the former simulation results. |
キーワード |
(和) |
ADPLL / PLL / Digital RF / Loop Filter / DCO / TDC / Sigma-Delta Modulation / |
(英) |
ADPLL / PLL / Digital RF / Loop Filter / DCO / TDC / Sigma-Delta Modulation / |
文献情報 |
信学技報, vol. 107, no. 162, SR2007-45, pp. 157-162, 2007年7月. |
資料番号 |
SR2007-45 |
発行日 |
2007-07-19 (SR) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
著作権に ついて |
技術研究報告に掲載された論文の著作権は電子情報通信学会に帰属します.(許諾番号:10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
PDFダウンロード |
SR2007-45 |