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Paper Abstract and Keywords
Presentation 2007-07-27 08:55
A 1GHz to 2GHz 4-Phase On-Chip Clock Generator with Timing Margin Test Capability
Shunichi Kaeriyama, Mikihiro Kajita, Masayuki Mizuno (NEC) ICD2007-55 Link to ES Tech. Rep. Archives: ICD2007-55
Abstract (in Japanese) (See Japanese page) 
(in English) A functional clock generator presented here makes timing margin testing possible. The clock generator provides the following functions: clock period adjustment, jitter generation, duty ratio adjustment, and clock skew adjustment, with 5ps resolution. The test chip fabricated with a 90nm CMOS occupies 300um x 128um die area and dissipates 40mW.
Keyword (in Japanese) (See Japanese page) 
(in English) Clock Generator / Timing Margin / Frequency Synthesis / Jitter / Duty / Skew / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 163, ICD2007-55, pp. 107-112, July 2007.
Paper # ICD2007-55 
Date of Issue 2007-07-19 (ICD) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ICD2007-55 Link to ES Tech. Rep. Archives: ICD2007-55

Conference Information
Committee ICD ITE-IST  
Conference Date 2007-07-26 - 2007-07-27 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
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Paper Information
Registration To ICD 
Conference Code 2007-07-ICD-ITE-IST 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A 1GHz to 2GHz 4-Phase On-Chip Clock Generator with Timing Margin Test Capability 
Sub Title (in English)  
Keyword(1) Clock Generator  
Keyword(2) Timing Margin  
Keyword(3) Frequency Synthesis  
Keyword(4) Jitter  
Keyword(5) Duty  
Keyword(6) Skew  
1st Author's Name Shunichi Kaeriyama  
1st Author's Affiliation NEC (NEC)
2nd Author's Name Mikihiro Kajita  
2nd Author's Affiliation NEC (NEC)
3rd Author's Name Masayuki Mizuno  
3rd Author's Affiliation NEC (NEC)
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Date Time 2007-07-27 08:55:00 
Presentation Time 25 
Registration for ICD 
Paper # IEICE-ICD2007-55 
Volume (vol) IEICE-107 
Number (no) no.163 
Page pp.107-112 
#Pages IEICE-6 
Date of Issue IEICE-ICD-2007-07-19 

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