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Paper Abstract and Keywords
Presentation 2007-07-27 11:10
Investigation of Parasitic Capacitance to Improve EMC Macro Model LECCS around 1GHz
Atsuhiro Takahashi, Kengo Iokibe (Okayama Univ.), Umberto Paoletti, Osami Wada (Kyoto Univ.), Yoshitaka Toyota, Ryuji Koga (Okayama Univ.) EMCJ2007-33 EMD2007-19 Link to ES Tech. Rep. Archives: EMD2007-19
Abstract (in Japanese) (See Japanese page) 
(in English) High frequency currents flowing in power supply networks of an IC/LSI has been estimated by an EMC macro model.
The high frequency currents due to the simultaneous switching noise of IC/LSI involving large amount of CMOS transistor is modeled with a linear equivalent circuit and current sources.
The linear equivalent circuit decreased its accuracy in impedance due to parasitic capacitances causing anti-resonances in the power supply networks.
This paper shows with results of experimental and numerical analysis that the parasitic capacitances on the package and printed circuit board
cause the anti-resonance.
The power supply network impedance were obtained experimentally by use of three evaluation boards with different parasitic capacitances.
The parasitic capacitances of the boards were calculated numerically by high-frequency electromagnetic analysis software Sonnet.
Impedance simulations by considering the parasitic capacitance shows that an appropriate connection of parasitic capacitances to the LECCS model can expand an available frequency range of the model beyond 1 GHz.
Keyword (in Japanese) (See Japanese page) 
(in English) Electromagnetic compatibility / CMOS IC / Power network impedance / LECCS model / Parasitic capacitance / Sonnet / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 167, EMCJ2007-33, pp. 5-10, July 2007.
Paper # EMCJ2007-33 
Date of Issue 2007-07-20 (EMCJ, EMD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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Download PDF EMCJ2007-33 EMD2007-19 Link to ES Tech. Rep. Archives: EMD2007-19

Conference Information
Committee EMCJ EMD  
Conference Date 2007-07-27 - 2007-07-27 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To EMCJ 
Conference Code 2007-07-EMCJ-EMD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Investigation of Parasitic Capacitance to Improve EMC Macro Model LECCS around 1GHz 
Sub Title (in English)  
Keyword(1) Electromagnetic compatibility  
Keyword(2) CMOS IC  
Keyword(3) Power network impedance  
Keyword(4) LECCS model  
Keyword(5) Parasitic capacitance  
Keyword(6) Sonnet  
Keyword(7)  
Keyword(8)  
1st Author's Name Atsuhiro Takahashi  
1st Author's Affiliation Okayama University (Okayama Univ.)
2nd Author's Name Kengo Iokibe  
2nd Author's Affiliation Okayama University (Okayama Univ.)
3rd Author's Name Umberto Paoletti  
3rd Author's Affiliation Kyoto University (Kyoto Univ.)
4th Author's Name Osami Wada  
4th Author's Affiliation Kyoto University (Kyoto Univ.)
5th Author's Name Yoshitaka Toyota  
5th Author's Affiliation Okayama University (Okayama Univ.)
6th Author's Name Ryuji Koga  
6th Author's Affiliation Okayama University (Okayama Univ.)
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Speaker Author-1 
Date Time 2007-07-27 11:10:00 
Presentation Time 25 minutes 
Registration for EMCJ 
Paper # EMCJ2007-33, EMD2007-19 
Volume (vol) vol.107 
Number (no) no.167(EMCJ), no.168(EMD) 
Page pp.5-10 
#Pages
Date of Issue 2007-07-20 (EMCJ, EMD) 


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