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Paper Abstract and Keywords
Presentation 2007-07-26 17:05
Low power consumption of H.264/AVC decoder with dynamic voltage and frequency scaling
Yoshinori Sakata, Kentaro Kawakami, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2007-52 Link to ES Tech. Rep. Archives: ICD2007-52
Abstract (in Japanese) (See Japanese page) 
(in English) We propose an elastic pipeline architecture that can apply dynamic voltage scaling (DVS) to a dedicated hardware, and apply the elastic pipeline to a portable H.264/AVC decoder LSI with embedded frame buffer SRAM. A supply voltage and operating frequency are controlled by a feedback-type voltage/frequency control algorithm for low-power operation. In a portable H.264/AVC decoder, embedded SRAM can be utilized as frame buffer since the frame buffer is not so large that an external DRAM is required. In the proposed elastic pipeline architecture, the power in the frame buffer SRAM and even in a local bus connecting with the frame buffer SRAM can be controlled by DVS. We carried out simulation in a 320 x 180 pixels and 320 x 240 pixels. The total power reductions in 320 x 180 pixels and 320 x 240 pixels are 30% and 30%.
Keyword (in Japanese) (See Japanese page) 
(in English) dynamic voltage scaling / elastic pipeline architecture / embedded SRAM / H.264/AVC / / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 163, ICD2007-52, pp. 89-94, July 2007.
Paper # ICD2007-52 
Date of Issue 2007-07-19 (ICD) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ICD2007-52 Link to ES Tech. Rep. Archives: ICD2007-52

Conference Information
Committee ICD ITE-IST  
Conference Date 2007-07-26 - 2007-07-27 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
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Paper Information
Registration To ICD 
Conference Code 2007-07-ICD-ITE-IST 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Low power consumption of H.264/AVC decoder with dynamic voltage and frequency scaling 
Sub Title (in English)  
Keyword(1) dynamic voltage scaling  
Keyword(2) elastic pipeline architecture  
Keyword(3) embedded SRAM  
Keyword(4) H.264/AVC  
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1st Author's Name Yoshinori Sakata  
1st Author's Affiliation Kobe University (Kobe Univ.)
2nd Author's Name Kentaro Kawakami  
2nd Author's Affiliation Kobe University (Kobe Univ.)
3rd Author's Name Hiroshi Kawaguchi  
3rd Author's Affiliation Kobe University (Kobe Univ.)
4th Author's Name Masahiko Yoshimoto  
4th Author's Affiliation Kobe University (Kobe Univ.)
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Speaker
Date Time 2007-07-26 17:05:00 
Presentation Time 25 
Registration for ICD 
Paper # IEICE-ICD2007-52 
Volume (vol) IEICE-107 
Number (no) no.163 
Page pp.89-94 
#Pages IEICE-6 
Date of Issue IEICE-ICD-2007-07-19 


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