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Paper Abstract and Keywords
Presentation 2007-07-26 17:30
A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing
Shunsuke Okumura, Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Yasuhiro Morita (Kobe Univ.), Koji Nii (Kobe Univ./Renesas Technology), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2007-53 Link to ES Tech. Rep. Archives: ICD2007-53
Abstract (in Japanese) (See Japanese page) 
(in English) We propose a low-power non-precharge-type two-port SRAM for video processing. The proposed memory cell (MC) has ten transistors (10T), comprised of the conventional 6T MC, a readout inverter and a transmission gate for a read port. Since the readout inverter fully charges/discharges a read bitline, there is no precharge circuit on the read bitline. Thus, power is not consumed by precharging. Besides, charge-less structure shortens a cycle time by 38% compared with the conventional SRAM, because it does not require a precharge period. Compared to the conventional 8T SRAM, the proposed SRAM reduces 81% of a charge/discharge possibility on the bitlines, and saves 74% of a readout power when considered as an H.264 reconstructed-image memory. The area overhead is 14.4% in a 90-nm process technology.
Keyword (in Japanese) (See Japanese page) 
(in English) Low-Power SRAM / non-precharge SRAM / two-port SRAM / video processing / H.264 / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 163, ICD2007-53, pp. 95-100, July 2007.
Paper # ICD2007-53 
Date of Issue 2007-07-19 (ICD) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (No. 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ICD2007-53 Link to ES Tech. Rep. Archives: ICD2007-53

Conference Information
Committee ICD ITE-IST  
Conference Date 2007-07-26 - 2007-07-27 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ICD 
Conference Code 2007-07-ICD-IST 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing 
Sub Title (in English)  
Keyword(1) Low-Power SRAM  
Keyword(2) non-precharge SRAM  
Keyword(3) two-port SRAM  
Keyword(4) video processing  
Keyword(5) H.264  
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Keyword(8)  
1st Author's Name Shunsuke Okumura  
1st Author's Affiliation Kobe University (Kobe Univ.)
2nd Author's Name Hiroki Noguchi  
2nd Author's Affiliation Kobe University (Kobe Univ.)
3rd Author's Name Yusuke Iguchi  
3rd Author's Affiliation Kobe University (Kobe Univ.)
4th Author's Name Hidehiro Fujiwara  
4th Author's Affiliation Kobe University (Kobe Univ.)
5th Author's Name Yasuhiro Morita  
5th Author's Affiliation Kobe University (Kobe Univ.)
6th Author's Name Koji Nii  
6th Author's Affiliation Kobe University/Renesas Technology (Kobe Univ./Renesas Technology)
7th Author's Name Hiroshi Kawaguchi  
7th Author's Affiliation Kobe University (Kobe Univ.)
8th Author's Name Masahiko Yoshimoto  
8th Author's Affiliation Kobe University (Kobe Univ.)
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Speaker
Date Time 2007-07-26 17:30:00 
Presentation Time 25 
Registration for ICD 
Paper # IEICE-ICD2007-53 
Volume (vol) IEICE-107 
Number (no) no.163 
Page pp.95-100 
#Pages IEICE-6 
Date of Issue IEICE-ICD-2007-07-19 


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