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| Presentation | 2007-07-20 11:35 Hardware Implementations of the 128-bit Blockcipher CLEFIA Taizo Shirai, Kyoji Shibutani, Toru Akishita, Shiho Moriai (Sony), Tetsu Iwata (Nagoya Univ.)  ISEC2007-49 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This paper presents optimization techniques and evaluation results in hardware implementations of the 128-bit blockcipher CLEFIA. We investigated efficient implementaions of two S-boxes and two diffusion matrices in $F$-functions, and the $DoubleSwap$ function used in the key scheduling part. Using a 0.09 $\mu$m CMOS ASIC library, our fast implementation and compact implementation of CLEFIA with 128-bit keys achieve 1.60 Gbps with less than 6 Kgate and 0.71 Gbps with less than 5 Kgate, respectively. These figures are so advantageous to the best known results of hardware performance of AES and Camellia that CLEFIA is a highly efficient blockcipher in hardware implementations. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | blockcipher / CLEFIA / hardware implementation / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 107, no. 141, ISEC2007-49, pp. 29-36, July 2007. | |
| Paper # | ISEC2007-49 | |
| Date of Issue | 2007-07-13 (ISEC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | ISEC2007-49 |
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| Conference Information | |
| Committee | ISEC SITE IPSJ-CSEC |
| Conference Date | 2007-07-19 - 2007-07-20 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Future University-Hakodate |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | ISEC |
| Conference Code | 2007-07-ISEC-SITE-IPSJ-CSEC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Hardware Implementations of the 128-bit Blockcipher CLEFIA |
| Sub Title (in English) | |
| Keyword(1) | blockcipher |
| Keyword(2) | CLEFIA |
| Keyword(3) | hardware implementation |
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| 1st Author's Name | Taizo Shirai |
| 1st Author's Affiliation | Sony Corporation (Sony) |
| 2nd Author's Name | Kyoji Shibutani |
| 2nd Author's Affiliation | Sony Corporation (Sony) |
| 3rd Author's Name | Toru Akishita |
| 3rd Author's Affiliation | Sony Corporation (Sony) |
| 4th Author's Name | Shiho Moriai |
| 4th Author's Affiliation | Sony Corporation (Sony) |
| 5th Author's Name | Tetsu Iwata |
| 5th Author's Affiliation | Nagoya University (Nagoya Univ.) |
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| Speaker | Author-3 |
| Date Time | 2007-07-20 11:35:00 |
| Presentation Time | 25 minutes |
| Registration for | ISEC |
| Paper # | ISEC2007-49 |
| Volume (vol) | vol.107 |
| Number (no) | no.141 |
| Page | pp.29-36 |
| #Pages | 8 |
| Date of Issue | 2007-07-13 (ISEC) |
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