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| Presentation | 2007-06-22 10:30 A Lateral Unified-CBiCMOS Buffer Circuit for Driving 5nF Maximum Load Capacitance per CCD Clock Masatoshi Kobayashi, Takashi Hamahata, Toshiro Akino, Kenji Nishi, Cuong Vo Le, Kousei Takehara, T. Goji Etoh (Kinki Univ.)  CAS2007-22 VLD2007-38 SIP2007-52 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Since 2001, we have been developing an in-situ storage image sensor (ISIS) that captures 100 to 150 consecutive images at a frame rate of 1 Mfps and an ultra-high-speed video camera for use with this ISIS. Currently, basic research is continuing in an attempt to increase the frame rate up to 100 Mfps. The CCD chip of this camera has a 10 V maximum voltage supply source and a 5 nF maximum load capacitance per CCD clock. The goal of this study is to design a prototype power supply chip for generating the CCD clock and for driving the load capacitance of the CCD chip. A further goal is to verify the circuit behavior, based on a 1-μm CMOS/SOI process having breakdown voltages of almost 20 V. A lateral unified-CBiCMOS buffer circuit consists of n- and p-channel MOSFETs that include parasitic lateral npn- and pnp-BJTs having partially depleted p- and n-base layers, respectively, on an epitaxial substrate and SOI. A forward current is applied to the base terminal of the channel MOSFET, adding a normal pull-up or pull-down MOSFET as a current source. A new device structure is designed to reduce the resistance values between the drains and the bases, while also keeping both MOSFETs inactive and activating either the lateral npn or pnp BJT. A clock generator consisting of a ring oscillator with a 21-stage CMOS inverter amplified and driven by a buffer circuit is designed. Circuit simulation using 1-μm LEVEL-3 model parameters for the MOSFETs and a current gain of βF = 100 for the BJTs reduced the delay time of the unified-CBiCMOS buffer circuit by approximately 1/4, compared to that for an equivalent two-stage CMOS inverter circuit designed on the basis of logical effort for driving a load capacitance of 5 nF at Vdd = 10 V. The power supply chip with the unified-CBiCMOS buffer circuit can drive the CCD chip at a frame rate of 10 Mfps for a 5-nF load capacitance | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Slanted linear CCD storage / ISIS / CMOS/SOI / Lateral unified-CBiCMOS / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 107, no. 103, VLD2007-38, pp. 19-24, June 2007. | |
| Paper # | VLD2007-38 | |
| Date of Issue | 2007-06-15 (CAS, VLD, SIP) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CAS2007-22 VLD2007-38 SIP2007-52 |
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| Conference Information | |
| Committee | CAS SIP VLD |
| Conference Date | 2007-06-21 - 2007-06-22 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Hokkaido Tokai Univ. （Sapporo) |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2007-06-CAS-SIP-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Lateral Unified-CBiCMOS Buffer Circuit for Driving 5nF Maximum Load Capacitance per CCD Clock |
| Sub Title (in English) | |
| Keyword(1) | Slanted linear CCD storage |
| Keyword(2) | ISIS |
| Keyword(3) | CMOS/SOI |
| Keyword(4) | Lateral unified-CBiCMOS |
| Keyword(5) | |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Masatoshi Kobayashi |
| 1st Author's Affiliation | Kinki University (Kinki Univ.) |
| 2nd Author's Name | Takashi Hamahata |
| 2nd Author's Affiliation | Kinki University (Kinki Univ.) |
| 3rd Author's Name | Toshiro Akino |
| 3rd Author's Affiliation | Kinki University (Kinki Univ.) |
| 4th Author's Name | Kenji Nishi |
| 4th Author's Affiliation | Kinki University (Kinki Univ.) |
| 5th Author's Name | Cuong Vo Le |
| 5th Author's Affiliation | Kinki University (Kinki Univ.) |
| 6th Author's Name | Kousei Takehara |
| 6th Author's Affiliation | Kinki University (Kinki Univ.) |
| 7th Author's Name | T. Goji Etoh |
| 7th Author's Affiliation | Kinki University (Kinki Univ.) |
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| Speaker | Author-1 |
| Date Time | 2007-06-22 10:30:00 |
| Presentation Time | 20 minutes |
| Registration for | VLD |
| Paper # | CAS2007-22, VLD2007-38, SIP2007-52 |
| Volume (vol) | vol.107 |
| Number (no) | no.101(CAS), no.103(VLD), no.105(SIP) |
| Page | pp.19-24 |
| #Pages | 6 |
| Date of Issue | 2007-06-15 (CAS, VLD, SIP) |
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