Paper Abstract and Keywords |
Presentation |
2007-06-21 14:10
Filter Design for Flexible Engine/Generic ALU Array and Its Dedicated Synthesis Algorithm Masayuki Honma, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Makoto Satoh (Hitachi) CAS2007-12 VLD2007-28 SIP2007-42 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Reconfigurable processors are processors whose contexts are dynamically reconfigured while they are working. We focus on a reconfigurable processor called FE-GA (Flexible Engine/Generic ALU array) for digital media processing. Presently, FE-GA do not have its dedicated development tool. Thus, in this paper, we design FIR filters and propose an algorithm to map them onto it automatically. For given a degree and coefficients of an FIR filter, the algorithm generates a dedicated assembly code which represents a given FIR filter for FE-GA. Then an editor called FEEditor reads the generated assembly code and implements its corresponding FIR filter on FE-GA. The proposed algorithm achieves automatic mapping of FIR filters of all degrees within the range of the specification of FE-GA architecture. Furthermore, it is proved that a minimum cycle to execute FIR filtering is achieved if there is no thread switch. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
reconfigurable processor / FE-GA / FIR filter / filter mapping / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 107, no. 102, VLD2007-28, pp. 67-72, June 2007. |
Paper # |
VLD2007-28 |
Date of Issue |
2007-06-14 (CAS, VLD, SIP) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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CAS2007-12 VLD2007-28 SIP2007-42 |
Conference Information |
Committee |
CAS SIP VLD |
Conference Date |
2007-06-21 - 2007-06-22 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Hokkaido Tokai Univ. (Sapporo) |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
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Paper Information |
Registration To |
VLD |
Conference Code |
2007-06-CAS-SIP-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Filter Design for Flexible Engine/Generic ALU Array and Its Dedicated Synthesis Algorithm |
Sub Title (in English) |
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Keyword(1) |
reconfigurable processor |
Keyword(2) |
FE-GA |
Keyword(3) |
FIR filter |
Keyword(4) |
filter mapping |
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1st Author's Name |
Masayuki Honma |
1st Author's Affiliation |
Waseda University (Waseda Univ.) |
2nd Author's Name |
Nozomu Togawa |
2nd Author's Affiliation |
Waseda University (Waseda Univ.) |
3rd Author's Name |
Masao Yanagisawa |
3rd Author's Affiliation |
Waseda University (Waseda Univ.) |
4th Author's Name |
Tatsuo Ohtsuki |
4th Author's Affiliation |
Waseda University (Waseda Univ.) |
5th Author's Name |
Makoto Satoh |
5th Author's Affiliation |
Hitachi, Ltd. (Hitachi) |
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Speaker |
Author-1 |
Date Time |
2007-06-21 14:10:00 |
Presentation Time |
20 minutes |
Registration for |
VLD |
Paper # |
CAS2007-12, VLD2007-28, SIP2007-42 |
Volume (vol) |
vol.107 |
Number (no) |
no.100(CAS), no.102(VLD), no.104(SIP) |
Page |
pp.67-72 |
#Pages |
6 |
Date of Issue |
2007-06-14 (CAS, VLD, SIP) |
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