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Paper Abstract and Keywords
Presentation 2007-06-07 13:30
Analysis of Electron and Hole Trap in MONOS-type Nonvolatile Memory
Takeshi Ishida, Renichi Yamada, Kazuyoshi Torii (Hitachi), Kenji Shiraishi (Univ. of Tsukuba) SDM2007-31 Link to ES Tech. Rep. Archives: SDM2007-31
Abstract (in Japanese) (See Japanese page) 
(in English) For the purpose of providing higher reliability to MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type nonvolatile memory, we have developed an analytical technique of the electron and hole trap distribution in the MONOS structure. Moreover, we have also developed a microscopic model of the origin of the charge trap. Electron and hole trap distributions were analyzed using a combination of avalanche charge injection and C-V measurement with varying thicknesses of the nitride layers in the MONOS structures. We have consequently found that electrons mainly located at both top and bottom oxide/nitride interfaces, whereas holes locate at the same interfaces as well as in the nitride bulk. We also found that the electron and hole traps are originated from 3-fold coordinated oxygen and silicon dangling bond respectively.
Keyword (in Japanese) (See Japanese page) 
(in English) MONOS / SONOS / Trap / Distribution / Energy level / Avalanche injection / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 85, SDM2007-31, pp. 1-6, June 2007.
Paper # SDM2007-31 
Date of Issue 2007-05-31 (SDM) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SDM2007-31 Link to ES Tech. Rep. Archives: SDM2007-31

Conference Information
Committee SDM  
Conference Date 2007-06-07 - 2007-06-08 
Place (in Japanese) (See Japanese page) 
Place (in English) Hiroshima Univ. ( Faculty Club) 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Sci. & Technol. for Thin Dielectrics for MIS Devices 
Paper Information
Registration To SDM 
Conference Code 2007-06-SDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Analysis of Electron and Hole Trap in MONOS-type Nonvolatile Memory 
Sub Title (in English)  
Keyword(1) MONOS  
Keyword(2) SONOS  
Keyword(3) Trap  
Keyword(4) Distribution  
Keyword(5) Energy level  
Keyword(6) Avalanche injection  
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Keyword(8)  
1st Author's Name Takeshi Ishida  
1st Author's Affiliation Hitachi, Ltd., Central Research Laboratory (Hitachi)
2nd Author's Name Renichi Yamada  
2nd Author's Affiliation Hitachi, Ltd., Central Research Laboratory (Hitachi)
3rd Author's Name Kazuyoshi Torii  
3rd Author's Affiliation Hitachi, Ltd., Central Research Laboratory (Hitachi)
4th Author's Name Kenji Shiraishi  
4th Author's Affiliation University of Tsukuba (Univ. of Tsukuba)
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Speaker Author-1 
Date Time 2007-06-07 13:30:00 
Presentation Time 25 minutes 
Registration for SDM 
Paper # SDM2007-31 
Volume (vol) vol.107 
Number (no) no.85 
Page pp.1-6 
#Pages
Date of Issue 2007-05-31 (SDM) 


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