Paper Abstract and Keywords |
Presentation |
2007-05-31 14:15
A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption Kiyoshi Hayase, Yutaka Yoshida, Tatsuya Kamei, Shinichi Shibahara, Osamu Nishii, Toshihiro Hattori, Atsushi Hasegawa (Renesas technology), Masashi Takada, Naohiko Irie, Kunio Uchiyama, Toshihiko Odaka (Hitachi Ltd.), Kiwamu Takada (Hitachi ULSI Systems Co. Ltd.), Keiji Kimura, Hironori Kasahara (Waseda Univ.) ICD2007-22 Link to ES Tech. Rep. Archives: ICD2007-22 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
4320MIPS 4-processor SoC that provides with low power consumption and high performance was designed using 90nm process. The 32KB-data cache is built into each processor, and the module to maintain the coherency of the data cache between processors is built into. A low electric power is achieved by frequency control of each processor according to amount of processing and adopting sleep mode that maintains coherency of the data cache between processors. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
multi processor / individually managed clock frequency / cache coherency / MESI protocol / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 107, no. 76, ICD2007-22, pp. 31-35, May 2007. |
Paper # |
ICD2007-22 |
Date of Issue |
2007-05-24 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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ICD2007-22 Link to ES Tech. Rep. Archives: ICD2007-22 |
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