IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2007-05-11 11:45
On power-conscious approach for prefix graph synthesis
Taeko Matsunaga (Waseda Univ), Yusuke Matsunaga (Kyushu Univ.)
Abstract (in Japanese) (See Japanese page) 
(in English) A prefix graph visualizes a global structure of a parallel prefix
adder at technology independent level. Several approaches on prefix
graph synthesis targeting area and delay minimization have been
proposed so far, but there are few for power.
In this paper, switching activity for each node of prefix graph is
targeted as one of power measures at technology-independent level. We
expand our timing-constrained area minimization algorithm
to treat switching activities as the cost to be minimized. Switching
activities are calculated by BDD-based method. Effects and issues of
our approach are discussed through experimental results.
Keyword (in Japanese) (See Japanese page) 
(in English) arithmetic synthesis / parallel prefix adder / low power / switching activity / dynamic programming / / /  
Reference Info. IEICE Tech. Rep., vol. 107, pp. 31-36, May 2007.
Paper #  
Date of Issue 2007-05-04 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Download PDF

Conference Information
Committee VLD IPSJ-SLDM  
Conference Date 2007-05-10 - 2007-05-11 
Place (in Japanese) (See Japanese page) 
Place (in English) Kyodai Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English) System Design, etc. 
Paper Information
Registration To IPSJ-SLDM 
Conference Code 2007-05-VLD-IPSJ-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) On power-conscious approach for prefix graph synthesis 
Sub Title (in English)  
Keyword(1) arithmetic synthesis  
Keyword(2) parallel prefix adder  
Keyword(3) low power  
Keyword(4) switching activity  
Keyword(5) dynamic programming  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Taeko Matsunaga  
1st Author's Affiliation Waseda University (Waseda Univ)
2nd Author's Name Yusuke Matsunaga  
2nd Author's Affiliation Kyushu University (Kyushu Univ.)
3rd Author's Name  
3rd Author's Affiliation ()
4th Author's Name  
4th Author's Affiliation ()
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker Author-1 
Date Time 2007-05-11 11:45:00 
Presentation Time 25 minutes 
Registration for IPSJ-SLDM 
Paper # VLD2007-12 
Volume (vol) vol.107 
Number (no) no.32 
Page pp.31-36 
#Pages
Date of Issue 2007-05-04 (VLD) 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan