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| Presentation | 2007-04-20 13:45 Soft Error Hardend Latch Scheme for Enhanced Scan Based Delay Fault Testing Takashi Ikeda, Kazuteru Namba, Hideo Ito (Chiba Univ.)  CPSY2007-1 DC2007-1 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In recent high-density, high-speed and low-power VLSIs, soft errors and delay faults frequently occur. Therefore, soft error hardened design and delay fault testing are essential. This paper proposes a latch scheme which has soft error tolerant capability and allows enhanced scan based delay fault testing. The proposed latch is constructed by added some extra transistors which make enhanced scan based delay fault testing possible into an existing soft error hardened latch. The proposed scheme allows not only arbitrary two-pattern testing but also detecting some stuck-at faults which is not detectable without the extra transistors. The area and time overhead of the proposed latch is up to 33.3% and 40.1% larger than those of the existing soft error hardened latch respectively. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Soft Error / Delay Fault / Enhanced Scan / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 107, no. 17, DC2007-1, pp. 1-6, April 2007. | |
| Paper # | DC2007-1 | |
| Date of Issue | 2007-04-13 (CPSY, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CPSY2007-1 DC2007-1 |
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| Conference Information | |
| Committee | CPSY DC |
| Conference Date | 2007-04-20 - 2007-04-20 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2007-04-CPSY-DC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Soft Error Hardend Latch Scheme for Enhanced Scan Based Delay Fault Testing |
| Sub Title (in English) | |
| Keyword(1) | Soft Error |
| Keyword(2) | Delay Fault |
| Keyword(3) | Enhanced Scan |
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| 1st Author's Name | Takashi Ikeda |
| 1st Author's Affiliation | Chiba University (Chiba Univ.) |
| 2nd Author's Name | Kazuteru Namba |
| 2nd Author's Affiliation | Chiba University (Chiba Univ.) |
| 3rd Author's Name | Hideo Ito |
| 3rd Author's Affiliation | Chiba University (Chiba Univ.) |
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| Speaker | Author-1 |
| Date Time | 2007-04-20 13:45:00 |
| Presentation Time | 30 minutes |
| Registration for | DC |
| Paper # | CPSY2007-1, DC2007-1 |
| Volume (vol) | vol.107 |
| Number (no) | no.16(CPSY), no.17(DC) |
| Page | pp.1-6 |
| #Pages | 6 |
| Date of Issue | 2007-04-13 (CPSY, DC) |
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