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Paper Abstract and Keywords
Presentation 2007-04-20 14:15
A scheduling algorithm in high-level synthesis for soft error tolerance with chained operations
Shintaro Imamura, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) CPSY2007-2 DC2007-2
Abstract (in Japanese) (See Japanese page) 
(in English) Soft errors refer to intermittent malfunctions, which are not physical defects.
Due to the high speed and low voltage operation of VLSIs, soft errors caused by particle strikes on combinational logics cannot be disregarded, not just on memory elements.
According to the model of soft errors presented in [1], focusing on the observation that a logic chain attenuates the noise caused by a particle strike on the logics, we propose a heuristic algorithm of scheduling in high-level synthesis for reducing the soft error rate.
Several case studies show that the proposed algorithm can effectively reduce the soft error rate while achieving minimum latencies under resource constraints.
Keyword (in Japanese) (See Japanese page) 
(in English) High-level synthesis / Soft error / Chaining / Scheduling / / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 17, DC2007-2, pp. 7-12, April 2007.
Paper # DC2007-2 
Date of Issue 2007-04-13 (CPSY, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee CPSY DC  
Conference Date 2007-04-20 - 2007-04-20 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
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Paper Information
Registration To DC 
Conference Code 2007-04-CPSY-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A scheduling algorithm in high-level synthesis for soft error tolerance with chained operations 
Sub Title (in English)  
Keyword(1) High-level synthesis  
Keyword(2) Soft error  
Keyword(3) Chaining  
Keyword(4) Scheduling  
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1st Author's Name Shintaro Imamura  
1st Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
2nd Author's Name Hideyuki Ichihara  
2nd Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
3rd Author's Name Tomoo Inoue  
3rd Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
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Speaker Author-1 
Date Time 2007-04-20 14:15:00 
Presentation Time 30 minutes 
Registration for DC 
Paper # CPSY2007-2, DC2007-2 
Volume (vol) vol.107 
Number (no) no.16(CPSY), no.17(DC) 
Page pp.7-12 
#Pages
Date of Issue 2007-04-13 (CPSY, DC) 


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