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| Presentation | 2007-04-12 14:20 A voltage scalable advanced DFM RAM with accelerated screening for low power SoC platform Hiroki Shimano, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto (Renesas Technology Corp.)  ICD2007-8 Link to ES Tech. Rep. Archives: ICD2007-8 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | The advanced-DFM (Design For Manufacturability) RAM provides the solution for the limitation of SRAM voltage scaling down and the countermeasure of the process fluctuations. The characteristics of this RAM are the voltage scalability (@0.6V operation) with wide operating margin and the reliability of long data retention time. The memory cell consists of 2Cell/bit with the complementary dynamic memory operation and has the 1Cell//bit test mode for the accelerated screening against the marginal cells. The GND bitline pre-charge sensing scheme and SSW(Sense Synchronized Write) peripheral circuit technologies are also adopted. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | DFM RAM / 2cell/bit / low voltage scalability / screening test / SoC memory platform / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 107, no. 1, ICD2007-8, pp. 41-46, April 2007. | |
| Paper # | ICD2007-8 | |
| Date of Issue | 2007-04-05 (ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | ICD2007-8 Link to ES Tech. Rep. Archives: ICD2007-8 |
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| Conference Information | |
| Committee | ICD |
| Conference Date | 2007-04-12 - 2007-04-13 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2007-04-ICD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A voltage scalable advanced DFM RAM with accelerated screening for low power SoC platform |
| Sub Title (in English) | |
| Keyword(1) | DFM RAM |
| Keyword(2) | 2cell/bit |
| Keyword(3) | low voltage scalability |
| Keyword(4) | screening test |
| Keyword(5) | SoC memory platform |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Hiroki Shimano |
| 1st Author's Affiliation | Renesas Technology Corp. (Renesas Technology Corp.) |
| 2nd Author's Name | Fukashi Morishita |
| 2nd Author's Affiliation | Renesas Technology Corp. (Renesas Technology Corp.) |
| 3rd Author's Name | Katsumi Dosaka |
| 3rd Author's Affiliation | Renesas Technology Corp. (Renesas Technology Corp.) |
| 4th Author's Name | Kazutami Arimoto |
| 4th Author's Affiliation | Renesas Technology Corp. (Renesas Technology Corp.) |
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| Speaker | Author-1 |
| Date Time | 2007-04-12 14:20:00 |
| Presentation Time | 30 minutes |
| Registration for | ICD |
| Paper # | ICD2007-8 |
| Volume (vol) | vol.107 |
| Number (no) | no.1 |
| Page | pp.41-46 |
| #Pages | 6 |
| Date of Issue | 2007-04-05 (ICD) |
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