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| Presentation | 2007-03-09 08:40 Easily Testable Multiplier with 4-2 Adder Tree Nobutaka Kito, Kensuke Hanai, Naofumi Takagi (Nagoya Univ.) Link to ES Tech. Rep. Archives:  ICD2006-231 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | The growth of the scale of VLSI designs makes test cost of VLSI chips expensive. Techniques of test cost reduction are required. A multiplier with a 4-2 adder tree, which is fast and has simple VLSI layout, is useful for a high-speed datapath. We present an easily testable multiplier with a 4-2 adder tree, with respect to the Cell Fault Model (CFM). We treat full adders as cells. We demonstrate a 4-2 adder tree, which has recursive configuration by unificating connection manner between 4-2 adders, has a test set which is derived recursively and whose size is independent of depth of the tree. Also, we demonstrate a design method of a partial product generation circuit to test a 4-2 adder tree through it. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | test generation / multiplier / C-testability / 4-2 adder tree / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 106, no. 549, VLD2006-140, pp. 1-6, March 2007. | |
| Paper # | VLD2006-140 | |
| Date of Issue | 2007-03-02 (VLD, ICD) | |
| ISSN | Print edition: ISSN 0913-5685 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | Link to ES Tech. Rep. Archives: ICD2006-231 |
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| Conference Information | |
| Committee | ICD VLD |
| Conference Date | 2007-03-07 - 2007-03-09 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Mielparque Okinawa |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | System-on-silicon design techniques and related VLSs |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2007-03-ICD-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Easily Testable Multiplier with 4-2 Adder Tree |
| Sub Title (in English) | |
| Keyword(1) | test generation |
| Keyword(2) | multiplier |
| Keyword(3) | C-testability |
| Keyword(4) | 4-2 adder tree |
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| Keyword(8) | |
| 1st Author's Name | Nobutaka Kito |
| 1st Author's Affiliation | Nagoya University (Nagoya Univ.) |
| 2nd Author's Name | Kensuke Hanai |
| 2nd Author's Affiliation | Nagoya University (Nagoya Univ.) |
| 3rd Author's Name | Naofumi Takagi |
| 3rd Author's Affiliation | Nagoya University (Nagoya Univ.) |
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| Speaker | Author-1 |
| Date Time | 2007-03-09 08:40:00 |
| Presentation Time | 20 minutes |
| Registration for | VLD |
| Paper # | VLD2006-140, ICD2006-231 |
| Volume (vol) | vol.106 |
| Number (no) | no.549(VLD), no.552(ICD) |
| Page | pp.1-6 |
| #Pages | 6 |
| Date of Issue | 2007-03-02 (VLD, ICD) |
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