Paper Abstract and Keywords |
Presentation |
2007-03-08 15:30
Design Method of Radix Converters Using Arithmetic Decompositions (3) Yukihiro Iguchi (Meiji Univ.), Tsutomu Sasao, Munehiro Matsuura (KIT), Toshikazu Aoyama (Meiji Univ.) Link to ES Tech. Rep. Archives: ICD2006-226 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In digital signal processing, radixes other than two are often used
for high-speed computation.
In the computation for finance, decimal numbers are used
instead of binary numbers.
In such cases, radix converters are necessary.
%In general, radix converters are complex.
Design methods for binary to $q$-nary converters were presented by us.
It introduced a new design technique based on weighted-sum (WS) functions.
We compute a WS function for each digit by an LUT cascade and a binary adder,
then add adjacent digits with $q$-nary adders.
We developed a synthesis tool which produces Verilog-HDL files and
data patterns of embedded memories on FPGAs.
A $16$-bit binary to decimal converter is designed to show the tool. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
radix converter / LUT cascade / arithmetic decomposition / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 106, no. 548, VLD2006-135, pp. 97-102, March 2007. |
Paper # |
VLD2006-135 |
Date of Issue |
2007-03-01 (VLD, ICD) |
ISSN |
Print edition: ISSN 0913-5685 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
Link to ES Tech. Rep. Archives: ICD2006-226 |
Conference Information |
Committee |
ICD VLD |
Conference Date |
2007-03-07 - 2007-03-09 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Mielparque Okinawa |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
System-on-silicon design techniques and related VLSs |
Paper Information |
Registration To |
VLD |
Conference Code |
2007-03-ICD-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Design Method of Radix Converters Using Arithmetic Decompositions (3) |
Sub Title (in English) |
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Keyword(1) |
radix converter |
Keyword(2) |
LUT cascade |
Keyword(3) |
arithmetic decomposition |
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1st Author's Name |
Yukihiro Iguchi |
1st Author's Affiliation |
Meiji University (Meiji Univ.) |
2nd Author's Name |
Tsutomu Sasao |
2nd Author's Affiliation |
Kyushu Institute of Technology (KIT) |
3rd Author's Name |
Munehiro Matsuura |
3rd Author's Affiliation |
Kyushu Institute of Technology (KIT) |
4th Author's Name |
Toshikazu Aoyama |
4th Author's Affiliation |
Meiji University (Meiji Univ.) |
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Speaker |
Author-1 |
Date Time |
2007-03-08 15:30:00 |
Presentation Time |
20 minutes |
Registration for |
VLD |
Paper # |
VLD2006-135, ICD2006-226 |
Volume (vol) |
vol.106 |
Number (no) |
no.548(VLD), no.551(ICD) |
Page |
pp.97-102 |
#Pages |
6 |
Date of Issue |
2007-03-01 (VLD, ICD) |
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