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| Presentation | 2007-03-08 14:30 Relocation Method for Circuit Modification Kunihiko Yanagibashi, Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC) Link to ES Tech. Rep. Archives:  ICD2006-224 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In this paper, we propose a novel migration method when the circuit with its placement is modified. In the method, its output placement keeps the structure of the original placement, called model placement, as possible. For the purpose, We minimize the total amount of displacement between the model placement and the relocated placement. Moreover, to archive a short run-time and efficiency, we employ the limitation of solution space and the change of packing origin in the optimization process. We construct the system on Sequence-Pair. Experimental results show that our approach preserves the chip area and the overall circuit structure with 98% less run-time than that by an ordinary Simulated Annealing. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Non full-reverse-order constraint / Circuit Modification / Relocation / Sequence-Pair / Simulated Annealing / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 106, no. 548, VLD2006-133, pp. 85-90, March 2007. | |
| Paper # | VLD2006-133 | |
| Date of Issue | 2007-03-01 (VLD, ICD) | |
| ISSN | Print edition: ISSN 0913-5685 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | Link to ES Tech. Rep. Archives: ICD2006-224 |
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| Conference Information | |
| Committee | ICD VLD |
| Conference Date | 2007-03-07 - 2007-03-09 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Mielparque Okinawa |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | System-on-silicon design techniques and related VLSs |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2007-03-ICD-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Relocation Method for Circuit Modification |
| Sub Title (in English) | |
| Keyword(1) | Non full-reverse-order constraint |
| Keyword(2) | Circuit Modification |
| Keyword(3) | Relocation |
| Keyword(4) | Sequence-Pair |
| Keyword(5) | Simulated Annealing |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Kunihiko Yanagibashi |
| 1st Author's Affiliation | The University of Kitakyushu (Univ. of Kitakyushu) |
| 2nd Author's Name | Yasuhiro Takashima |
| 2nd Author's Affiliation | The University of Kitakyushu (Univ. of Kitakyushu) |
| 3rd Author's Name | Yuichi Nakamura |
| 3rd Author's Affiliation | NEC (NEC) |
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| Speaker | Author-1 |
| Date Time | 2007-03-08 14:30:00 |
| Presentation Time | 20 minutes |
| Registration for | VLD |
| Paper # | VLD2006-133, ICD2006-224 |
| Volume (vol) | vol.106 |
| Number (no) | no.548(VLD), no.551(ICD) |
| Page | pp.85-90 |
| #Pages | 6 |
| Date of Issue | 2007-03-01 (VLD, ICD) |
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