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| Paper Abstract and Keywords | ||
| Presentation | 2007-03-08 17:10 [Invited Talk] Measurements and reduction of power line noises in SoCs Makoto Ikeda, Kunihiro Asada (Tokyo Univ.) Link to ES Tech. Rep. Archives:  ICD2006-230 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This paper describes power bounce measurement technique in SoCs and active substrate noise reduction techniques. Noise measurement techniques are categorized into time-domain noise measurement techniques, frequency-domain noise/jitter measurement techniques. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Power line noise / Substrate noise / Noise sampling / Noise waveform / Noise spectrum / Power integrity / / | |
| Reference Info. | IEICE Tech. Rep., vol. 106, no. 551, ICD2006-230, pp. 121-126, March 2007. | |
| Paper # | ICD2006-230 | |
| Date of Issue | 2007-03-01 (VLD, ICD) | |
| ISSN | Print edition: ISSN 0913-5685 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | Link to ES Tech. Rep. Archives: ICD2006-230 |
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| Conference Information | |
| Committee | ICD VLD |
| Conference Date | 2007-03-07 - 2007-03-09 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Mielparque Okinawa |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | System-on-silicon design techniques and related VLSs |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2007-03-ICD-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Measurements and reduction of power line noises in SoCs |
| Sub Title (in English) | |
| Keyword(1) | Power line noise |
| Keyword(2) | Substrate noise |
| Keyword(3) | Noise sampling |
| Keyword(4) | Noise waveform |
| Keyword(5) | Noise spectrum |
| Keyword(6) | Power integrity |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Makoto Ikeda |
| 1st Author's Affiliation | University of Tokyo (Tokyo Univ.) |
| 2nd Author's Name | Kunihiro Asada |
| 2nd Author's Affiliation | University of Tokyo (Tokyo Univ.) |
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| Speaker | Author-1 |
| Date Time | 2007-03-08 17:10:00 |
| Presentation Time | 50 minutes |
| Registration for | ICD |
| Paper # | VLD2006-139, ICD2006-230 |
| Volume (vol) | vol.106 |
| Number (no) | no.548(VLD), no.551(ICD) |
| Page | pp.121-126 |
| #Pages | 6 |
| Date of Issue | 2007-03-01 (VLD, ICD) |
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