Paper Abstract and Keywords |
Presentation |
2007-03-07 17:00
On-chip monitoring for sub-100-nm digital signal integrity Yoji Bando, Koichiro Noguchi, Makoto Nagata (Kobe Univ.) Link to ES Tech. Rep. Archives: ICD2006-207 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
A compact on-chip signal monitor circuit uses voltage mode sensing by a source follower circuit with small input device geometry, followed by a shared current output bus. A prototype signal monitor circuit demonstrated a 1.1-GHz effective bandwidth for 1.0-V full-swing digital signals in a 90-nm CMOS technology, where the monitor used 2.5-V I/O CMOS transistors and occupied a 30$\mu$m×120$\mu$m silicon area. We also showed that such signal monitor ciucuits can be tailored to sense of power supply, ground, as well as full-swing logic signal wirings, and form an array with a single current output. Therefore, an on-chip multi-channel signal monitor enables multiple-points as well as multiple-voltagedomain waveform acquisition for the purpose of the in-depth study of digital signal integrity. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
signal integrity / dynamic power supply noise / delay variation / on-chip monitor / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 106, no. 550, ICD2006-207, pp. 61-66, March 2007. |
Paper # |
ICD2006-207 |
Date of Issue |
2007-02-28 (VLD, ICD) |
ISSN |
Print edition: ISSN 0913-5685 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
Link to ES Tech. Rep. Archives: ICD2006-207 |
Conference Information |
Committee |
ICD VLD |
Conference Date |
2007-03-07 - 2007-03-09 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Mielparque Okinawa |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
System-on-silicon design techniques and related VLSs |
Paper Information |
Registration To |
ICD |
Conference Code |
2007-03-ICD-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
On-chip monitoring for sub-100-nm digital signal integrity |
Sub Title (in English) |
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signal integrity |
Keyword(2) |
dynamic power supply noise |
Keyword(3) |
delay variation |
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on-chip monitor |
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1st Author's Name |
Yoji Bando |
1st Author's Affiliation |
Kobe University (Kobe Univ.) |
2nd Author's Name |
Koichiro Noguchi |
2nd Author's Affiliation |
Kobe University (Kobe Univ.) |
3rd Author's Name |
Makoto Nagata |
3rd Author's Affiliation |
Kobe University (Kobe Univ.) |
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Speaker |
Author-1 |
Date Time |
2007-03-07 17:00:00 |
Presentation Time |
20 minutes |
Registration for |
ICD |
Paper # |
VLD2006-116, ICD2006-207 |
Volume (vol) |
vol.106 |
Number (no) |
no.547(VLD), no.550(ICD) |
Page |
pp.61-66 |
#Pages |
6 |
Date of Issue |
2007-02-28 (VLD, ICD) |
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