| Conference Information |
| Committee |
CAS |
| Conference Date |
2007-01-29 - 2007-01-30 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
Ehime Univ. |
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
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| Paper Information |
| Registration To |
CAS |
| Conference Code |
2007-01-CAS |
| Language |
English |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
A Test Generation Framework using Checker Circuits and its Application to Path Delay Test Generation |
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| 1st Author's Name |
Tsuyoshi Iwagaki |
| 1st Author's Affiliation |
Japan Advanced Institute of Science and Technology (JAIST) |
| 2nd Author's Name |
Satoshi Ohtake |
| 2nd Author's Affiliation |
Nara Institute of Science and Technology (NAIST) |
| 3rd Author's Name |
Mineo Kaneko |
| 3rd Author's Affiliation |
Japan Advanced Institute of Science and Technology (JAIST) |
| 4th Author's Name |
Hideo Fujiwara |
| 4th Author's Affiliation |
Nara Institute of Science and Technology (NAIST) |
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| Speaker |
Author-1 |
| Date Time |
2007-01-30 12:20:00 |
| Presentation Time |
25 minutes |
| Registration for |
CAS |
| Paper # |
CAS2006-76 |
| Volume (vol) |
vol.106 |
| Number (no) |
no.512 |
| Page |
pp.37-42 |
| #Pages |
6 |
| Date of Issue |
2007-01-23 (CAS) |