| Conference Information |
| Committee |
VLD CPSY RECONF IPSJ-SLDM |
| Conference Date |
2007-01-17 - 2007-01-18 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
Keio Univ. Hiyoshi Campus |
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
FPGA and its Application, etc. |
| Paper Information |
| Registration To |
VLD |
| Conference Code |
2007-01-VLD-CPSY-RECONF-IPSJ-SLDM |
| Language |
Japanese |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
Design of Residue Dividers Using Signed-Digit Number Residue Addition |
| Sub Title (in English) |
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| Keyword(1) |
modular division |
| Keyword(2) |
module addition |
| Keyword(3) |
VHDL |
| Keyword(4) |
signed-digit number |
| Keyword(5) |
residue number system |
| Keyword(6) |
Montgomery |
| Keyword(7) |
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| Keyword(8) |
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| 1st Author's Name |
Peng Jia |
| 1st Author's Affiliation |
Gunma University (Gunma Univ.) |
| 2nd Author's Name |
Shugang Wei |
| 2nd Author's Affiliation |
Gunma University (Gunma Univ.) |
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| Speaker |
Author-1 |
| Date Time |
2007-01-17 14:50:00 |
| Presentation Time |
25 minutes |
| Registration for |
VLD |
| Paper # |
VLD2006-88, CPSY2006-59, RECONF2006-59 |
| Volume (vol) |
vol.106 |
| Number (no) |
no.453(VLD), no.455(CPSY), no.457(RECONF) |
| Page |
pp.19-24 |
| #Pages |
6 |
| Date of Issue |
2007-01-10 (VLD, CPSY, RECONF) |