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Paper Abstract and Keywords
Presentation 2006-11-30 09:25
Architecture Design for Low-Power Multiplier applying Run Time Power Gating
Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Naoaki Ohkubo, Kimiyoshi Usami (S.I.T)
Abstract (in Japanese) (See Japanese page) 
(in English) (Not available yet)
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(in English) / / / / / / /  
Reference Info. IEICE Tech. Rep., vol. 106, no. 389, VLD2006-73, pp. 7-12, Nov. 2006.
Paper # VLD2006-73 
Date of Issue 2006-11-23 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685
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Conference Information
Committee RECONF CPSY VLD DC IPSJ-SLDM IPSJ-ARC  
Conference Date 2006-11-28 - 2006-11-30 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitakyushu International Conference Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2006 ---A New Frontier in VLSI Design--- 
Paper Information
Registration To VLD 
Conference Code 2006-11-RECONF-CPSY-VLD-DC-IPSJ-SLDM-IPSJ-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Architecture Design for Low-Power Multiplier applying Run Time Power Gating 
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1st Author's Name Toshihiro Kashima  
1st Author's Affiliation Shibaura Institute of Technology (S.I.T)
2nd Author's Name Seidai Takeda  
2nd Author's Affiliation Shibaura Institute of Technology (S.I.T)
3rd Author's Name Toshiaki Shirai  
3rd Author's Affiliation Shibaura Institute of Technology (S.I.T)
4th Author's Name Naoaki Ohkubo  
4th Author's Affiliation Shibaura Institute of Technology (S.I.T)
5th Author's Name Kimiyoshi Usami  
5th Author's Affiliation Shibaura Institute of Technology (S.I.T)
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Date Time 2006-11-30 09:25:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2006-73, DC2006-60 
Volume (vol) vol.106 
Number (no) no.389(VLD), no.392(DC) 
Page pp.7-12 
#Pages
Date of Issue 2006-11-23 (VLD, DC) 


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