IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2006-10-27 10:30
Design Method of System LSI with Three-Dimensional Transistor (FinFET) -- Reduction of pattern Area --
Shigeyoshi Watanabe, Keisuke Okamoto, Makoto Oya (SIT) Link to ES Tech. Rep. Archives: ICD2006-131
Abstract (in Japanese) (See Japanese page) 
(in English) New design method of system LSI with FinFET has been developed. Using planar+FinFET architecture the pattern area of system LSI designed by cell library can be reduced to about 30% compared with the conventional planar case. New design method is a promising candidate for realizing future high performance, high-density system LSI.
Keyword (in Japanese) (See Japanese page) 
(in English) system LSI / FinFET / channel width / sidewall channel width / cell library / TIS / /  
Reference Info. IEICE Tech. Rep., vol. 106, no. 317, ICD2006-131, pp. 25-30, Oct. 2006.
Paper # ICD2006-131 
Date of Issue 2006-10-20 (SIP, ICD, IE) 
ISSN Print edition: ISSN 0913-5685
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF Link to ES Tech. Rep. Archives: ICD2006-131

Conference Information
Committee ICD SIP IE IPSJ-SLDM  
Conference Date 2006-10-26 - 2006-10-27 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ICD 
Conference Code 2006-10-ICD-SIP-IE-IPSJ-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design Method of System LSI with Three-Dimensional Transistor (FinFET) 
Sub Title (in English) Reduction of pattern Area 
Keyword(1) system LSI  
Keyword(2) FinFET  
Keyword(3) channel width  
Keyword(4) sidewall channel width  
Keyword(5) cell library  
Keyword(6) TIS  
Keyword(7)  
Keyword(8)  
1st Author's Name Shigeyoshi Watanabe  
1st Author's Affiliation Shonan Institute of Technology (SIT)
2nd Author's Name Keisuke Okamoto  
2nd Author's Affiliation Shonan Institute of Technology (SIT)
3rd Author's Name Makoto Oya  
3rd Author's Affiliation Shonan Institute of Technology (SIT)
4th Author's Name  
4th Author's Affiliation ()
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker Author-1 
Date Time 2006-10-27 10:30:00 
Presentation Time 20 minutes 
Registration for ICD 
Paper # SIP2006-105, ICD2006-131, IE2006-83 
Volume (vol) vol.106 
Number (no) no.315(SIP), no.317(ICD), no.319(IE) 
Page pp.25-30 
#Pages
Date of Issue 2006-10-20 (SIP, ICD, IE) 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan