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| Presentation | 2006-10-27 10:50 Design method of low-power dual-supply-voltage system LSI taking into account leakage current of MOSFET Shigeyoshi Watanabe, Masaki Kanai, Akira Nagasawa, Satoshi Hanami, Manabu Kobayashi, Toshinori Takabatake (SIT) Link to ES Tech. Rep. Archives:  ICD2006-132 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Reduction of power dissipation caused by dynamic current, gate leakage current, and subthreshold leakage current of dual-supply-voltage (VH, VL) system LSI has been analyzed. The reduction ratio of power dissipation due to leakage current is strongly depend on VH. Not only dynamic current but also leakage current can be successfully reduced with using conventional dual-supply- voltage scheme for 32nm-65nm generation. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | system LSI / dual supply voltage scheme / dynamic current / gate leakage current / subthreshold leakage current / MOSFET / scaling rule / path-delay distribution | |
| Reference Info. | IEICE Tech. Rep., vol. 106, no. 317, ICD2006-132, pp. 31-36, Oct. 2006. | |
| Paper # | ICD2006-132 | |
| Date of Issue | 2006-10-20 (SIP, ICD, IE) | |
| ISSN | Print edition: ISSN 0913-5685 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | Link to ES Tech. Rep. Archives: ICD2006-132 |
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| Conference Information | |
| Committee | ICD SIP IE IPSJ-SLDM |
| Conference Date | 2006-10-26 - 2006-10-27 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2006-10-ICD-SIP-IE-IPSJ-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design method of low-power dual-supply-voltage system LSI taking into account leakage current of MOSFET |
| Sub Title (in English) | |
| Keyword(1) | system LSI |
| Keyword(2) | dual supply voltage scheme |
| Keyword(3) | dynamic current |
| Keyword(4) | gate leakage current |
| Keyword(5) | subthreshold leakage current |
| Keyword(6) | MOSFET |
| Keyword(7) | scaling rule |
| Keyword(8) | path-delay distribution |
| 1st Author's Name | Shigeyoshi Watanabe |
| 1st Author's Affiliation | Shonan Institute of Technology (SIT) |
| 2nd Author's Name | Masaki Kanai |
| 2nd Author's Affiliation | Shonan Institute of Technology (SIT) |
| 3rd Author's Name | Akira Nagasawa |
| 3rd Author's Affiliation | Shonan Institute of Technology (SIT) |
| 4th Author's Name | Satoshi Hanami |
| 4th Author's Affiliation | Shonan Institute of Technology (SIT) |
| 5th Author's Name | Manabu Kobayashi |
| 5th Author's Affiliation | Shonan Institute of Technology (SIT) |
| 6th Author's Name | Toshinori Takabatake |
| 6th Author's Affiliation | Shonan Institute of Technology (SIT) |
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| Speaker | Author-1 |
| Date Time | 2006-10-27 10:50:00 |
| Presentation Time | 20 minutes |
| Registration for | ICD |
| Paper # | SIP2006-106, ICD2006-132, IE2006-84 |
| Volume (vol) | vol.106 |
| Number (no) | no.315(SIP), no.317(ICD), no.319(IE) |
| Page | pp.31-36 |
| #Pages | 6 |
| Date of Issue | 2006-10-20 (SIP, ICD, IE) |
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