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| Paper Abstract and Keywords | ||
| Presentation | 2006-10-27 09:20 On synthesis algorithm for parallel prefix adders using dynamic programming Taeko Matsunaga (FLEETS), Yusuke Matsunaga (Kyushu Univ.) Link to ES Tech. Rep. Archives:  ICD2006-128 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This paper addresses parallel prefix adder synthesis which targets area minimization under given timing constraints. This problem is treated as synthesis of prefix graphs, which represent global structures of parallel prefix adders, and an algorithm using dynamic programming is proposed. Contributions are to enable dynamic programming to be applied efficiently by introducing and utilizing an appropriate constraints for prefix graphs, and to apply heuristics which reduce the number of nodes by relaxing the constraints. Experimental results show that the number of nodes of generated prefix graphs can be reduced by about 10%, and area after logic synthesis can be reduced by about 35% than existing methods. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | arithmetic synthesis / parallel prefix adder / dynamic programming / logic synthesis / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 106, pp. 7-12, Oct. 2006. | |
| Paper # | ||
| Date of Issue | 2006-10-20 (SIP, ICD, IE) | |
| ISSN | Print edition: ISSN 0913-5685 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | Link to ES Tech. Rep. Archives: ICD2006-128 |
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| Conference Information | |
| Committee | ICD SIP IE IPSJ-SLDM |
| Conference Date | 2006-10-26 - 2006-10-27 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | IPSJ-SLDM |
| Conference Code | 2006-10-ICD-SIP-IE-IPSJ-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | On synthesis algorithm for parallel prefix adders using dynamic programming |
| Sub Title (in English) | |
| Keyword(1) | arithmetic synthesis |
| Keyword(2) | parallel prefix adder |
| Keyword(3) | dynamic programming |
| Keyword(4) | logic synthesis |
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| 1st Author's Name | Taeko Matsunaga |
| 1st Author's Affiliation | FLEETS (FLEETS) |
| 2nd Author's Name | Yusuke Matsunaga |
| 2nd Author's Affiliation | Kyushu University (Kyushu Univ.) |
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| Speaker | Author-1 |
| Date Time | 2006-10-27 09:20:00 |
| Presentation Time | 20 minutes |
| Registration for | IPSJ-SLDM |
| Paper # | SIP2006-102, ICD2006-128, IE2006-80 |
| Volume (vol) | vol.106 |
| Number (no) | no.315(SIP), no.317(ICD), no.319(IE) |
| Page | pp.7-12 |
| #Pages | 6 |
| Date of Issue | 2006-10-20 (SIP, ICD, IE) |
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