Paper Abstract and Keywords |
Presentation |
2006-10-26 11:30
Super parallel SIMD processor with CAM based high-speed pattern matching capability Yutaka Kono, Takeshi Kumaki, Masakatsu Ishizaki, Masaharu Tagami, Tetsushi Koide, Hans Juergen Mattausch (Hiroshima Univ.), Takayuki Gyohten, Hideyuki Noda, Yasuto Kuroda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito (Renesas) Link to ES Tech. Rep. Archives: ICD2006-116 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
A super parallel SIMD processor has been developed for handling the increasing amount of
multimedia data efficiently.
It is able to execute the same operation with a large amount of multimedia data at high speed
by changing the conventional word-serial processing to a highly parallel bit-serial
processing with a large number of simple computing units.
In this paper, we improve the time space conversion bus bridge (TS-bridge), which is the
external interface of the super parallel SIMD processor,
with a pattern matching capability for table look-up operations.
This reduces the number of Huffman coding
clock cycles by 60% as compared with DSP because the necessary
can be carried out in table look-up clock cycles. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
super parallel SIMD processor / CAM / Huffman encoding / multimedia processing / pattern matching / / / |
Reference Info. |
IEICE Tech. Rep., vol. 106, no. 316, ICD2006-116, pp. 39-44, Oct. 2006. |
Paper # |
ICD2006-116 |
Date of Issue |
2006-10-19 (SIP, ICD, IE) |
ISSN |
Print edition: ISSN 0913-5685 |
Copyright and reproduction |
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