| 講演抄録／キーワード |
| 講演名 |
2006-09-15 11:45
A Parametric Study of Packet-Switched FPGA Overlay Networks
○Daihan Wang・Hiroki Matsutani・Masato Yoshimi（Keio Univ.）・Michihiro Koibuchi（NII）・Hideharu Amano（Keio Univ.） |
| 抄録 |
（和） |
(まだ登録されていません) |
| （英） |
The constantly upgrading gate capacity of FPGAs
enables us to implement a complex system on a chip.
A packet-switched network presents to share
network resources by multiple connections, so as to
make the best use of link bandwidth.
This study investigates the suitable
overlay interconnects on FPGAs in terms of the amount of hardware, and
throughput based on a parametric approach.
Because the number of ports on a router sometimes dominates the amount of hardware
for router, and its throughput performance, it has been chosen as a
parameter. Based on a typical implementation of NoC router,
various networks have been generalized and evaluated, in the case of both 16 hosts
and 36 hosts.
Evaluation results show that for small systems with 16 hosts or less,
a full-crossbar switch is advantageous from the viewpoint of both
throughput performance and hardware cost.
On the other hand, when systems become large,
the partitioned networks are efficient from the viewpoint of hardware cost.
When the performance requirement is not so critical, we should
select partitioned topology which requires minimum hardware and use some
localization methods to improve the performance. |
| キーワード |
（和） |
/ / / / / / / |
| （英） |
FPGA / Networks-on-chip / Router / Node degree / Simulation / / / |
| 文献情報 |
信学技報, vol. 106, no. 247, RECONF2006-32, pp. 31-36, 2006年9月. |
| 資料番号 |
RECONF2006-32 |
| 発行日 |
2006-09-08 (RECONF) |
| ISSN |
Print edition: ISSN 0913-5685 |
| PDFダウンロード |
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