Paper Abstract and Keywords |
Presentation |
2006-08-18 09:00
A Test Structure to Separately Analyze CMOSFET Reliabilities along The Channel Width Takashi Ohzone, Eiji Ishii, Takayuki Morishita, Kiyotaka Komoku (Okayama Pref. Univ.), Toshihiro Matsuda, Hideyuki Iwata (Toyama Pref. Univ.) Link to ES Tech. Rep. Archives: SDM2006-142 ICD2006-96 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
A test structure with four kinds of MOSFETs(i.e., [A]([D]) with a short(long) channel-length all over the channel width, [B]([C]) with the short(long) and the long(short) channel-length around the center and the both isolation-edges, respectively) was proposed to separately analyze the location where the hot-carrier-induced CMOSFET reliability is determined around the center or the isolation-edge along the channel-width. The reliability data were almost categorized into three (i.e., [A], [B]/[C] and [D]), which mean that the reliabilities are nearly the same around center or isolation-edge for the CMOSFETs. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
CMOSFET / reliability / LDD-type / channel width / isolation / / / |
Reference Info. |
IEICE Tech. Rep., vol. 106, no. 206, SDM2006-142, pp. 99-104, Aug. 2006. |
Paper # |
SDM2006-142 |
Date of Issue |
2006-08-10 (SDM, ICD) |
ISSN |
Print edition: ISSN 0913-5685 |
Copyright and reproduction |
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Link to ES Tech. Rep. Archives: SDM2006-142 ICD2006-96 |
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