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Paper Abstract and Keywords
Presentation 2006-08-18 11:40
Embedded Bulk FinFET SRAM Cell Technology with Planar FET Peripheral Circuit for hp32 nm node and beyond
Hirohisa Kawasaki (TAEC), Satoshi Inaba, Kimitoshi Okano, Akio Kaneko (Toshiba Semicon.), Atsushi Yagishita (TAEC), Takashi Izumida, Takahisa Kanemura, Takahiko Sasaki, Nobuaki Otsuka, Nobutoshi Aoki, Kyoichi Suguro, Kazuhiro Eguchi, Yoshitaka Tsunashima (Toshiba Semicon.), Kazunari Ishimaru (TAEC), Hidemi Ishiuchi (Toshiba Semicon.) Link to ES Tech. Rep. Archives: SDM2006-147 ICD2006-101
Abstract (in Japanese) (See Japanese page) 
(in English) (Not available yet)
Keyword (in Japanese) (See Japanese page) 
(in English) / / / / / / /  
Reference Info. IEICE Tech. Rep., vol. 106, no. 206, SDM2006-147, pp. 127-132, Aug. 2006.
Paper # SDM2006-147 
Date of Issue 2006-08-10 (SDM, ICD) 
ISSN Print edition: ISSN 0913-5685
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF Link to ES Tech. Rep. Archives: SDM2006-147 ICD2006-101

Conference Information
Committee ICD SDM  
Conference Date 2006-08-17 - 2006-08-18 
Place (in Japanese) (See Japanese page) 
Place (in English) Hokkaido University 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To SDM 
Conference Code 2006-08-ICD-SDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Embedded Bulk FinFET SRAM Cell Technology with Planar FET Peripheral Circuit for hp32 nm node and beyond 
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1st Author's Name Hirohisa Kawasaki  
1st Author's Affiliation Toshiba America Electronic Components, Inc. (TAEC)
2nd Author's Name Satoshi Inaba  
2nd Author's Affiliation Toshiba Corporation Semiconductor Company (Toshiba Semicon.)
3rd Author's Name Kimitoshi Okano  
3rd Author's Affiliation Toshiba Corporation Semiconductor Company (Toshiba Semicon.)
4th Author's Name Akio Kaneko  
4th Author's Affiliation Toshiba Corporation Semiconductor Company (Toshiba Semicon.)
5th Author's Name Atsushi Yagishita  
5th Author's Affiliation Toshiba America Electronic Components, Inc. (TAEC)
6th Author's Name Takashi Izumida  
6th Author's Affiliation Toshiba Corporation Semiconductor Company (Toshiba Semicon.)
7th Author's Name Takahisa Kanemura  
7th Author's Affiliation Toshiba Corporation Semiconductor Company (Toshiba Semicon.)
8th Author's Name Takahiko Sasaki  
8th Author's Affiliation Toshiba Corporation Semiconductor Company (Toshiba Semicon.)
9th Author's Name Nobuaki Otsuka  
9th Author's Affiliation Toshiba Corporation Semiconductor Company (Toshiba Semicon.)
10th Author's Name Nobutoshi Aoki  
10th Author's Affiliation Toshiba Corporation Semiconductor Company (Toshiba Semicon.)
11th Author's Name Kyoichi Suguro  
11th Author's Affiliation Toshiba Corporation Semiconductor Company (Toshiba Semicon.)
12th Author's Name Kazuhiro Eguchi  
12th Author's Affiliation Toshiba Corporation Semiconductor Company (Toshiba Semicon.)
13th Author's Name Yoshitaka Tsunashima  
13th Author's Affiliation Toshiba Corporation Semiconductor Company (Toshiba Semicon.)
14th Author's Name Kazunari Ishimaru  
14th Author's Affiliation Toshiba America Electronic Components, Inc. (TAEC)
15th Author's Name Hidemi Ishiuchi  
15th Author's Affiliation Toshiba Corporation Semiconductor Company (Toshiba Semicon.)
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Date Time 2006-08-18 11:40:00 
Presentation Time 25 minutes 
Registration for SDM 
Paper # SDM2006-147, ICD2006-101 
Volume (vol) vol.106 
Number (no) no.206(SDM), no.207(ICD) 
Page pp.127-132 
#Pages
Date of Issue 2006-08-10 (SDM, ICD) 


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