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Paper Abstract and Keywords
Presentation 2006-06-23 11:10
Reductions for Monotone Boolean Circuits
Kazuo Iwama, Hiroki Morizumi (Kyoto Univ.)
Abstract (in Japanese) (See Japanese page) 
(in English) The large class, say {\it NLOG}, of Boolean functions, including 0-1 Sort and 0-1 Merge, have an upper bound of $O(n\log n)$ for their monotone circuit size, i.e., have circuits with $O(n\log n)$ AND/OR gates of fan-in two. Suppose that we can use, besides such normal AND/OR gates, any number of more powerful ``$F$-gates'' which realize a monotone Boolean function $F$ with $r (\geq 2)$ inputs and $r' (\geq 1)$ outputs. Note that the cost of each AND/OR gate is one and we assume that the cost of each $F$-gate is $r$. Now we define: A Boolean function $f$ in NLOG is said to be $F$-Easy if $f$ can be computed by a circuit with AND/OR/$F$ gates whose total cost is $o(n\log n)$. In this paper we show that 0-1 Merge is not $F$-Easy for an arbitrary monotone function $F$ such that $r' \leq r/\log r$.
Keyword (in Japanese) (See Japanese page) 
(in English) circuit complexity / monotone circuit / lower bound / merging function / majority function / / /  
Reference Info. IEICE Tech. Rep., vol. 106, no. 128, COMP2006-19, pp. 15-19, June 2006.
Paper # COMP2006-19 
Date of Issue 2006-06-16 (COMP) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380

Conference Information
Committee COMP  
Conference Date 2006-06-23 - 2006-06-23 
Place (in Japanese) (See Japanese page) 
Place (in English) Saitama Univ. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To COMP 
Conference Code 2006-06-COMP 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Reductions for Monotone Boolean Circuits 
Sub Title (in English)  
Keyword(1) circuit complexity  
Keyword(2) monotone circuit  
Keyword(3) lower bound  
Keyword(4) merging function  
Keyword(5) majority function  
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1st Author's Name Kazuo Iwama  
1st Author's Affiliation Kyoto University (Kyoto Univ.)
2nd Author's Name Hiroki Morizumi  
2nd Author's Affiliation Kyoto University (Kyoto Univ.)
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Speaker
Date Time 2006-06-23 11:10:00 
Presentation Time 35 
Registration for COMP 
Paper # IEICE-COMP2006-19 
Volume (vol) IEICE-106 
Number (no) no.128 
Page pp.15-19 
#Pages IEICE-5 
Date of Issue IEICE-COMP-2006-06-16 


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