| Paper Abstract and Keywords |
| Presentation |
2006-06-22 13:30
Area/delay Estimation for Application Processor
Daisuke Yamazaki, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
This paper proposes an area/delay estimation method with configurable pipeline stages and controller structure.In HW/SW cosynthesis, we optimize processor architecture for a target application, and design a hardware part and a software part at the same time.In order to obtain an optimal architecture processor in a short time, we require a fast area/delay estimation method without logic synthesis in an architecture exploration phase.It is important to estimate them accurately because a large range of errors may lead an inadequate solution. In the proposal method, we partition the processor core into several functional parts and parameterize them, and obtain an estimation equation by analyzing the results of logic synthesis.We show the effectiveness of the proposal technique by verifying the area/delay values obtained from the equation estimation and the logic synthesis value of the processor core. Relative error of them is 1.13[%] on the average.Errors of delays is 0.14[ns] on the average. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
area/delay estimation / hardware/software cosynthesis / application processor / / / / / |
| Reference Info. |
IEICE Tech. Rep., vol. 106, no. 113, VLD2006-14, pp. 1-6, June 2006. |
| Paper # |
VLD2006-14 |
| Date of Issue |
2006-06-15 (CAS, VLD, SIP) |
| ISSN |
Print edition: ISSN 0913-5685 |
| Download PDF |
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| Conference Information |
| Committee |
SIP CAS VLD |
| Conference Date |
2006-06-22 - 2006-06-23 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
Kitami Institute of Technology |
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
Signal Processing, LSI, etc |
| Paper Information |
| Registration To |
VLD |
| Conference Code |
2006-06-SIP-CAS-VLD |
| Language |
Japanese |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
Area/delay Estimation for Application Processor |
| Sub Title (in English) |
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| Keyword(1) |
area/delay estimation |
| Keyword(2) |
hardware/software cosynthesis |
| Keyword(3) |
application processor |
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| 1st Author's Name |
Daisuke Yamazaki |
| 1st Author's Affiliation |
Waseda University (Waseda Univ.) |
| 2nd Author's Name |
Shunitsu Kohara |
| 2nd Author's Affiliation |
Waseda University (Waseda Univ.) |
| 3rd Author's Name |
Nozomu Togawa |
| 3rd Author's Affiliation |
Waseda University (Waseda Univ.) |
| 4th Author's Name |
Masao Yanagisawa |
| 4th Author's Affiliation |
Waseda University (Waseda Univ.) |
| 5th Author's Name |
Tatsuo Ohtsuki |
| 5th Author's Affiliation |
Waseda University (Waseda Univ.) |
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| Speaker |
Author-1 |
| Date Time |
2006-06-22 13:30:00 |
| Presentation Time |
25 minutes |
| Registration for |
VLD |
| Paper # |
CAS2006-1, VLD2006-14, SIP2006-24 |
| Volume (vol) |
vol.106 |
| Number (no) |
no.111(CAS), no.113(VLD), no.115(SIP) |
| Page |
pp.1-6 |
| #Pages |
6 |
| Date of Issue |
2006-06-15 (CAS, VLD, SIP) |