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Paper Abstract and Keywords
Presentation 2006-06-09 14:00
Design of a High Performance Vision Processor with Shared Memory Multi-SIMD Architecture
Kota Yamaguchi, Yoshihiro Watanabe, Takashi Komuro, Masatoshi Ishikawa (The University of Tokyo) Link to ES Tech. Rep. Archives: ICD2006-56
Abstract (in Japanese) (See Japanese page) 
(in English) For high speed image recognition in real environment, it is a challenge to accelerate a large amount of calculation for image processing from pre-processing to feature extraction. We designed a vision processor which consists of 2D / 1D parallel SIMD and 0D sequential processor modules that share a memory. The processor has summation and broadcast function between modules, which accelerates complicated operations in image processing. Memory sharing reduces cost for data transferring between modules and simplifies implementation of various parallel algorithms. Simulation results show the processor can perform various image processings with much less operation steps.
Keyword (in Japanese) (See Japanese page) 
(in English) massively parallel processing / SIMD / image recognition LSI / / / / /  
Reference Info. IEICE Tech. Rep., vol. 106, no. 92, ICD2006-56, pp. 89-94, June 2006.
Paper # ICD2006-56 
Date of Issue 2006-06-01 (ICD) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee ICD IPSJ-ARC  
Conference Date 2006-06-08 - 2006-06-09 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
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Paper Information
Registration To ICD 
Conference Code 2006-06-ICD-IPSJ-ARC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design of a High Performance Vision Processor with Shared Memory Multi-SIMD Architecture 
Sub Title (in English)  
Keyword(1) massively parallel processing  
Keyword(2) SIMD  
Keyword(3) image recognition LSI  
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1st Author's Name Kota Yamaguchi  
1st Author's Affiliation Graduate School of Information Science and Technology, The University of Tokyo (The University of Tokyo)
2nd Author's Name Yoshihiro Watanabe  
2nd Author's Affiliation Graduate School of Information Science and Technology, The University of Tokyo (The University of Tokyo)
3rd Author's Name Takashi Komuro  
3rd Author's Affiliation Graduate School of Information Science and Technology, The University of Tokyo (The University of Tokyo)
4th Author's Name Masatoshi Ishikawa  
4th Author's Affiliation Graduate School of Information Science and Technology, The University of Tokyo (The University of Tokyo)
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Speaker
Date Time 2006-06-09 14:00:00 
Presentation Time 30 
Registration for ICD 
Paper # IEICE-ICD2006-56 
Volume (vol) IEICE-106 
Number (no) no.92 
Page pp.89-94 
#Pages IEICE-6 
Date of Issue IEICE-ICD-2006-06-01 


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