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| Paper Abstract and Keywords | ||
| Presentation | 2006-04-14 11:15 DRAM技術を用いた16M SRAM Yuji Kihara, Yasushi Nakashima, Takashi Izutsu, Masayuki Nakamoto (Renesas), Tsutomu Yoshihara (Waseda Univ.) Link to ES Tech. Rep. Archives:  ICD2006-15 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | A 16Mbit Low Power SRAM with 0.98um2 cells using 0.15um DRAM and TFT technology has been developed. A new type memory cell technology achieves enough low power, low cost and high soft error immunity without large investment. By these improved characteristics some customers at industrial machines and handy devices decided to use this new type of SRAM by compatibility with SRAM. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | SRAM / SuperSRAM / Soft error free / Low voltage operation / Small size SRAM memory cell / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 106, no. 2, ICD2006-15, pp. 81-84, April 2006. | |
| Paper # | ICD2006-15 | |
| Date of Issue | 2006-04-06 (ICD) | |
| ISSN | Print edition: ISSN 0913-5685 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | Link to ES Tech. Rep. Archives: ICD2006-15 |
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| Conference Information | |
| Committee | ICD |
| Conference Date | 2006-04-13 - 2006-04-14 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Oita University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2006-04-ICD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | DRAM技術を用いた16M SRAM |
| Sub Title (in English) | |
| Keyword(1) | SRAM |
| Keyword(2) | SuperSRAM |
| Keyword(3) | Soft error free |
| Keyword(4) | Low voltage operation |
| Keyword(5) | Small size SRAM memory cell |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Yuji Kihara |
| 1st Author's Affiliation | Renesas Technology (Renesas) |
| 2nd Author's Name | Yasushi Nakashima |
| 2nd Author's Affiliation | Renesas Technology (Renesas) |
| 3rd Author's Name | Takashi Izutsu |
| 3rd Author's Affiliation | Renesas Technology (Renesas) |
| 4th Author's Name | Masayuki Nakamoto |
| 4th Author's Affiliation | Renesas Technology (Renesas) |
| 5th Author's Name | Tsutomu Yoshihara |
| 5th Author's Affiliation | Waseda University Graduated School (Waseda Univ.) |
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| Speaker | Author-1 |
| Date Time | 2006-04-14 11:15:00 |
| Presentation Time | 25 minutes |
| Registration for | ICD |
| Paper # | ICD2006-15 |
| Volume (vol) | vol.106 |
| Number (no) | no.2 |
| Page | pp.81-84 |
| #Pages | 4 |
| Date of Issue | 2006-04-06 (ICD) |
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