Paper Abstract and Keywords |
Presentation |
2006-04-13 09:45
A 65nm Low-Power Embedded DRAM with Extended Data-Retention Sleep Mode Tomohisa Takai, Takeshi Nagai, Masaharu Wada, Hitoshi Iwai, Mariko Kaku, Atsushi Suzuki, Naoko Itoga, Takayuki Miyazaki (Toshiba), Hiroyuki Takenaka (Toshiba Microelectronics), Takehiko Hojo, Shinji Miyano (Toshiba) Link to ES Tech. Rep. Archives: ICD2006-2 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
An Extended Data Retention (EDR) sleep mode with on-chip ECC and the MT-CMOS technique is proposed for the embedded DRAM stand-by power reduction. In the sleep mode, the retention time is 8 times longer by ECC and the leakage current is reduced to less than 13% compared with normal operation mode. Since ECC operates only in the EDR sleep mode, read/write performance is not degraded. A 65nm low power embedded DRAM macro with 400MHz operation and 0.39mW of data retention power is realized. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Embedded DRAM / Low Power / ECC circuit / MT-CMOS technique / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 106, no. 2, ICD2006-2, pp. 7-12, April 2006. |
Paper # |
ICD2006-2 |
Date of Issue |
2006-04-06 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 |
Copyright and reproduction |
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