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Paper Abstract and Keywords
Presentation 2006-04-13 09:45
A 65nm Low-Power Embedded DRAM with Extended Data-Retention Sleep Mode
Tomohisa Takai, Takeshi Nagai, Masaharu Wada, Hitoshi Iwai, Mariko Kaku, Atsushi Suzuki, Naoko Itoga, Takayuki Miyazaki (Toshiba), Hiroyuki Takenaka (Toshiba Microelectronics), Takehiko Hojo, Shinji Miyano (Toshiba) Link to ES Tech. Rep. Archives: ICD2006-2
Abstract (in Japanese) (See Japanese page) 
(in English) An Extended Data Retention (EDR) sleep mode with on-chip ECC and the MT-CMOS technique is proposed for the embedded DRAM stand-by power reduction. In the sleep mode, the retention time is 8 times longer by ECC and the leakage current is reduced to less than 13% compared with normal operation mode. Since ECC operates only in the EDR sleep mode, read/write performance is not degraded. A 65nm low power embedded DRAM macro with 400MHz operation and 0.39mW of data retention power is realized.
Keyword (in Japanese) (See Japanese page) 
(in English) Embedded DRAM / Low Power / ECC circuit / MT-CMOS technique / / / /  
Reference Info. IEICE Tech. Rep., vol. 106, no. 2, ICD2006-2, pp. 7-12, April 2006.
Paper # ICD2006-2 
Date of Issue 2006-04-06 (ICD) 
ISSN Print edition: ISSN 0913-5685
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF Link to ES Tech. Rep. Archives: ICD2006-2

Conference Information
Committee ICD  
Conference Date 2006-04-13 - 2006-04-14 
Place (in Japanese) (See Japanese page) 
Place (in English) Oita University 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ICD 
Conference Code 2006-04-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A 65nm Low-Power Embedded DRAM with Extended Data-Retention Sleep Mode 
Sub Title (in English)  
Keyword(1) Embedded DRAM  
Keyword(2) Low Power  
Keyword(3) ECC circuit  
Keyword(4) MT-CMOS technique  
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Keyword(8)  
1st Author's Name Tomohisa Takai  
1st Author's Affiliation Toshiba Corporation (Toshiba)
2nd Author's Name Takeshi Nagai  
2nd Author's Affiliation Toshiba Corporation (Toshiba)
3rd Author's Name Masaharu Wada  
3rd Author's Affiliation Toshiba Corporation (Toshiba)
4th Author's Name Hitoshi Iwai  
4th Author's Affiliation Toshiba Corporation (Toshiba)
5th Author's Name Mariko Kaku  
5th Author's Affiliation Toshiba Corporation (Toshiba)
6th Author's Name Atsushi Suzuki  
6th Author's Affiliation Toshiba Corporation (Toshiba)
7th Author's Name Naoko Itoga  
7th Author's Affiliation Toshiba Corporation (Toshiba)
8th Author's Name Takayuki Miyazaki  
8th Author's Affiliation Toshiba Corporation (Toshiba)
9th Author's Name Hiroyuki Takenaka  
9th Author's Affiliation Toshiba Microelectronics Corporation (Toshiba Microelectronics)
10th Author's Name Takehiko Hojo  
10th Author's Affiliation Toshiba Corporation (Toshiba)
11th Author's Name Shinji Miyano  
11th Author's Affiliation Toshiba Corporation (Toshiba)
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Speaker Author-1 
Date Time 2006-04-13 09:45:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # ICD2006-2 
Volume (vol) vol.106 
Number (no) no.2 
Page pp.7-12 
#Pages
Date of Issue 2006-04-06 (ICD) 


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