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Paper Abstract and Keywords
Presentation 2006-03-10 14:25
A reconfigurable circuit to utilize and compensate device variations
Manabu Kotani, Kazuya Katsuki, Kosuke Ogata, Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto Univ.) Link to ES Tech. Rep. Archives: ICD2005-247
Abstract (in Japanese) (See Japanese page) 
(in English) This paper provides the principle and architecture of a reconfigurable circuit utilizing Within-Die variaitions and shows a experimental results of speed and yield enhancement.We designed and fabricated a FPGA with a functionality to measure variations with 2% of high accuracy.The overhead caused by the mechanism is regarded as sufficient small.
A verification with a simple model circuit shows that performance of the circuit is enhanced by 4% in average, which is the same amount as the width of variations.The yield is enhanced 32% to the worst case.
Keyword (in Japanese) (See Japanese page) 
(in English) variations / reconfigure / FPGA / DFM / / / /  
Reference Info. IEICE Tech. Rep., vol. 105, no. 647, ICD2005-247, pp. 49-54, March 2006.
Paper # ICD2005-247 
Date of Issue 2006-03-03 (VLD, ICD) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF Link to ES Tech. Rep. Archives: ICD2005-247

Conference Information
Committee ICD VLD  
Conference Date 2006-03-09 - 2006-03-10 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ICD 
Conference Code 2006-03-ICD-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A reconfigurable circuit to utilize and compensate device variations 
Sub Title (in English)  
Keyword(1) variations  
Keyword(2) reconfigure  
Keyword(3) FPGA  
Keyword(4) DFM  
1st Author's Name Manabu Kotani  
1st Author's Affiliation Kyoto University (Kyoto Univ.)
2nd Author's Name Kazuya Katsuki  
2nd Author's Affiliation Kyoto University (Kyoto Univ.)
3rd Author's Name Kosuke Ogata  
3rd Author's Affiliation Kyoto University (Kyoto Univ.)
4th Author's Name Kazutoshi Kobayashi  
4th Author's Affiliation Kyoto University (Kyoto Univ.)
5th Author's Name Hidetoshi Onodera  
5th Author's Affiliation Kyoto University (Kyoto Univ.)
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Date Time 2006-03-10 14:25:00 
Presentation Time 25 
Registration for ICD 
Paper # IEICE-VLD2005-130,IEICE-ICD2005-247 
Volume (vol) IEICE-105 
Number (no) no.645(VLD), no.647(ICD) 
Page pp.49-54 
#Pages IEICE-6 
Date of Issue IEICE-VLD-2006-03-03,IEICE-ICD-2006-03-03 

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