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Paper Abstract and Keywords
Presentation 2006-03-10 15:35
An On-chip PVT Control System for Worst-caseless Lower Voltage SoC Design
Takayuki Gyohten, Fukashi Morishita (Renesas Technology Corp.), Mako Okamoto (Daioh Electric Corp.), Katsumi Dosaka, Kazutami Arimoto (Renesas Technology Corp.) Link to ES Tech. Rep. Archives: ICD2005-249
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper, we propose on-chip PVT (process, voltage, and temperature) control system for worst-caseless lower voltage SoC design that consist of the adaptive voltage management (AVM). The proposed AVM accurately detects the temperature by two oscillators that have different temperature characteristics, and controls to set the most suitable voltage level with table look-up method. And AVM can be supplied higher drivability even at lower voltage by lowering operating point of the comparator in the regulator. The experimental chip is fabricated on 90nm CMOS process and confirmed the proposed architecture accurately controls the voltage level and the operation margin securing at the lower voltage.
Keyword (in Japanese) (See Japanese page) 
(in English) PVT variations / temperature detection / series regulator / / / / /  
Reference Info. IEICE Tech. Rep., vol. 105, no. 647, ICD2005-249, pp. 61-66, March 2006.
Paper # ICD2005-249 
Date of Issue 2006-03-03 (VLD, ICD) 
ISSN Print edition: ISSN 0913-5685
Copyright
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF Link to ES Tech. Rep. Archives: ICD2005-249

Conference Information
Committee ICD VLD  
Conference Date 2006-03-09 - 2006-03-10 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ICD 
Conference Code 2006-03-ICD-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An On-chip PVT Control System for Worst-caseless Lower Voltage SoC Design 
Sub Title (in English)  
Keyword(1) PVT variations  
Keyword(2) temperature detection  
Keyword(3) series regulator  
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1st Author's Name Takayuki Gyohten  
1st Author's Affiliation Renesas Technology Corporation (Renesas Technology Corp.)
2nd Author's Name Fukashi Morishita  
2nd Author's Affiliation Renesas Technology Corporation (Renesas Technology Corp.)
3rd Author's Name Mako Okamoto  
3rd Author's Affiliation Daioh Electric Corporation (Daioh Electric Corp.)
4th Author's Name Katsumi Dosaka  
4th Author's Affiliation Renesas Technology Corporation (Renesas Technology Corp.)
5th Author's Name Kazutami Arimoto  
5th Author's Affiliation Renesas Technology Corporation (Renesas Technology Corp.)
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Speaker Author-1 
Date Time 2006-03-10 15:35:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # VLD2005-132, ICD2005-249 
Volume (vol) vol.105 
Number (no) no.645(VLD), no.647(ICD) 
Page pp.61-66 
#Pages
Date of Issue 2006-03-03 (VLD, ICD) 


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