Paper Abstract and Keywords |
Presentation |
2006-01-26 16:10
Footless Dual-Rail Domino Circuit with Self-Timed Preharge Scheme in SOI Technology KinHooi Dia, Ruotong Zheng, Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo) Link to ES Tech. Rep. Archives: ICD2005-213 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This paper presents a new footless dual-rail domino circuit that efficiently combines a footless dynamic circuit technique with a robust self-timed precharge scheme for high performance VLSI design. Along with these, the proposed circuit achieves a whole footless dual-rail domino circuit with the use of the proposed separator. A 20-stage NAND chain with fan-out 8 is implemented in 0.15-um SOI CMOS technology for performance evaluation. Measurement results reveal that the proposed circuit achieves 2.57, 1.72 and 1.12 times speed improvement over the circuit implemented with CPL, the conventional static CMOS and the conventional dynamic DCVSL, respectively. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Footless Domino / Dual-Rail / Self-Timed Precharge / DCVSL / SOI / / / |
Reference Info. |
IEICE Tech. Rep., vol. 105, no. 569, ICD2005-213, pp. 47-51, Jan. 2006. |
Paper # |
ICD2005-213 |
Date of Issue |
2006-01-19 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
Link to ES Tech. Rep. Archives: ICD2005-213 |
Conference Information |
Committee |
ICD ITE-CE |
Conference Date |
2006-01-26 - 2006-01-27 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kikai-Shinko-Kaikan Bldg. |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
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Paper Information |
Registration To |
ICD |
Conference Code |
2006-01-ICD-ITE-CE |
Language |
English |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Footless Dual-Rail Domino Circuit with Self-Timed Preharge Scheme in SOI Technology |
Sub Title (in English) |
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Keyword(1) |
Footless Domino |
Keyword(2) |
Dual-Rail |
Keyword(3) |
Self-Timed Precharge |
Keyword(4) |
DCVSL |
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SOI |
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1st Author's Name |
KinHooi Dia |
1st Author's Affiliation |
University of Tokyo (Univ. of Tokyo) |
2nd Author's Name |
Ruotong Zheng |
2nd Author's Affiliation |
University of Tokyo (Univ. of Tokyo) |
3rd Author's Name |
Makoto Ikeda |
3rd Author's Affiliation |
University of Tokyo (Univ. of Tokyo) |
4th Author's Name |
Kunihiro Asada |
4th Author's Affiliation |
University of Tokyo (Univ. of Tokyo) |
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Speaker |
Author-1 |
Date Time |
2006-01-26 16:10:00 |
Presentation Time |
30 minutes |
Registration for |
ICD |
Paper # |
ICD2005-213 |
Volume (vol) |
vol.105 |
Number (no) |
no.569 |
Page |
pp.47-51 |
#Pages |
5 |
Date of Issue |
2006-01-19 (ICD) |