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| Presentation | 2006-01-26 10:30 Phase Change RAM Operated with 1.5-V CMOS as Low Cost Embedded Memory Satoru Hanzawa, Kenichi Osada, Takayuki Kawahara, Riichiro Takemura (Hitachi CRL), Naoki Kitai (Hitachi ULSI), Norikatsu Takaura, Nozomu Matsuzaki, Kenzo Kurotsuchi (Hitachi CRL), Hiroshi Moriya (Hitachi MERL), Masahiro Moniwa (Renesas) Link to ES Tech. Rep. Archives:  ICD2005-206 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This paper describes a phase change (PC) RAM operated at the lowest possible voltage, 1.5 V, with a CMOS memory array, using PC material with the lowest RESET current. We discuss the margins for RESET/SET/READ operations based on measurement results and identified that it is impossible to distinguish between RESET/SET operations by controlling the bit-line voltage. We propose a new tri-level voltage word-line control (3LV-WL) scheme to clearly operate SET operations. Moreover, we investigated the READ disturb operation and developed a new reduced-actual-READ-access (RA2) scheme to attain 500 times the READ retention time. We also developed a source line control (SLC) scheme to attain an 18% smaller cell size and a 19-F2 memory cell with enough RESET current to clearly reset the PC material. With the application of these approaches, we established RESET/SET/READ operations with the lowest possible voltage, 1.5 V with logic CMOS, for a low-cost embedded memory with a few additional masks. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Phase change / Embedded memory / Tri-level voltage word-line control scheme / Reduced-actual-READ-access scheme / Source line control scheme / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 105, no. 569, ICD2005-206, pp. 7-12, Jan. 2006. | |
| Paper # | ICD2005-206 | |
| Date of Issue | 2006-01-19 (ICD) | |
| ISSN | Print edition: ISSN 0913-5685 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | Link to ES Tech. Rep. Archives: ICD2005-206 |
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| Conference Information | |
| Committee | ICD ITE-CE |
| Conference Date | 2006-01-26 - 2006-01-27 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2006-01-ICD-ITE-CE |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Phase Change RAM Operated with 1.5-V CMOS as Low Cost Embedded Memory |
| Sub Title (in English) | |
| Keyword(1) | Phase change |
| Keyword(2) | Embedded memory |
| Keyword(3) | Tri-level voltage word-line control scheme |
| Keyword(4) | Reduced-actual-READ-access scheme |
| Keyword(5) | Source line control scheme |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Satoru Hanzawa |
| 1st Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. (Hitachi CRL) |
| 2nd Author's Name | Kenichi Osada |
| 2nd Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. (Hitachi CRL) |
| 3rd Author's Name | Takayuki Kawahara |
| 3rd Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. (Hitachi CRL) |
| 4th Author's Name | Riichiro Takemura |
| 4th Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. (Hitachi CRL) |
| 5th Author's Name | Naoki Kitai |
| 5th Author's Affiliation | Hitachi ULSI Systems Co. (Hitachi ULSI) |
| 6th Author's Name | Norikatsu Takaura |
| 6th Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. (Hitachi CRL) |
| 7th Author's Name | Nozomu Matsuzaki |
| 7th Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. (Hitachi CRL) |
| 8th Author's Name | Kenzo Kurotsuchi |
| 8th Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. (Hitachi CRL) |
| 9th Author's Name | Hiroshi Moriya |
| 9th Author's Affiliation | Mechanical Engineering Research Laboratory, Hitachi, Ltd. (Hitachi MERL) |
| 10th Author's Name | Masahiro Moniwa |
| 10th Author's Affiliation | Renesas Corp. (Renesas) |
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| Speaker | Author-1 |
| Date Time | 2006-01-26 10:30:00 |
| Presentation Time | 30 minutes |
| Registration for | ICD |
| Paper # | ICD2005-206 |
| Volume (vol) | vol.105 |
| Number (no) | no.569 |
| Page | pp.7-12 |
| #Pages | 6 |
| Date of Issue | 2006-01-19 (ICD) |
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